Oracle International Corporation

Oracle America, Inc.

Sambanova Systems, Inc.

Sun Microsystems, Inc.

Dawei Huang

Jianghui Su

Drew George Doblar

Deqiang Song

Manish K Shah

Emre Ali Burhan

Gregory Frederick Grohoski

Raghu Prabhakar

Sumti Jairath

Ram Sivaramakrishnan

Kin Hing Leung

Ravinder Kumar

Xun Zhang

Arnav Goel

Zuxu Qin

Ranen Chatterjee

Bandish B Shah

Muthukumar Vairavan

Manoj Unnikrishnan

Rajesh Kumar

Chaitanya Palusa

Nirmal Chindhu Warke

Gabriel C Risk

Michael Stephen Harwood

Yan Yan

Howard Lee Davidson

Paul Joseph Jordan

David K McElfresh

Martin Russell Raumann

Thomas M Wicki

Frankie Liu

Kannan Raj

Dong Joon Yoon

Waseem Ahmad

Philip P Kwan

Hongtao Zhang

Baoqing Huang

Osman Javed

Arif Al Amin

Seno Judaprawira

Suwen Yang

Wenhua Li

Pradeep Nagarajan

Andrew Keith Joy

Jing Shi

Nyles I Nettleton

Ben Chen

Vivek Nama

Long Kong

Natalie You

William Franklin Leven

Yizhou Jiang

Michelle L Wong

Jason H Bau

Jiangyuan Li

Albert Martin

Daniel J Beckman

Theresa Sze

Rick Lytel

Yong Qin

Kuai Yin

Maoqing Yao

Yuhan Yao

Ali Gokhan Ileri

Sifang You

Jihong Min

Nicholas E Aneshansley

Francis Schumacher

Simon Dennis Forey

Quang H Trang

Kunmo Kim

Venkatesh Arunachalam

A reconfigurable dataflow unit (RDU) includes an intra-RDU network, an array of configurable units connected by an array level network and function interfaces. The RDU also includes interface circuits coupled between the intra-RDU network and external interconnects. An interface circuit receives a packet from the external interconnect and extracts a target RDU identifier and compares the target RDU identifier to the value of the identity register. It also communicates over the intra-RDU network to a function interface based on information in the first packet in response to the target RDU identifier being equal to the identity register. The interface circuit retrieves another interface circuit identifier for the target RDU identifier from the pass-through table and, in response to the target RDU identifier not being equal to the identity register, sends the target RDU identifier and other information to the other interface circuit over the intra-RDU network.

Peer-to-peer route through in a reconfigurable computing system

The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using network interface controller (NIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and application data for applications using a first reconfigurable processor connected to a first host, and a second reconfigurable processor connected to a second host. The first reconfigurable processor is configured to push input data for the applications in a first plurality of buffers. The first host is configured to cause a first network interface controller (NIC) to stream the input data to a second plurality of buffers from the first plurality of buffers. The second host is configured to cause a second NIC to stream the input data to the second reconfigurable processor from the second plurality of buffers.

Inter-node execution of configuration files on reconfigurable processors using network interface controller (NIC) buffers

The technology disclosed relates to runtime execution of functions across reconfigurable processor. In particular, the technology disclosed relates to a runtime logic that is configured to execute a first set of functions in a plurality of functions and/or data therefor on a first reconfigurable processor, and a second set of functions in the plurality of functions and/or data therefor on additional reconfigurable processors. Functions in the second set of functions and/or the data therefor are transmitted to the additional reconfigurable processors using one or more of a first reconfigurable processor-to-additional reconfigurable processors buffers, and results of executing the functions and/or the data therefor on the additional reconfigurable processors are transmitted to the first reconfigurable processor using one or more of additional reconfigurable processors-to-first reconfigurable processor buffers.

Runtime execution of functions across reconfigurable processor

A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

Adaptive receiver with pre-cursor cancelation

The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor on a first node, and a second host processor on a second node. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second host processor using one or more SmartNIC buffers.

Inter-node execution of configuration files on reconfigurable processors using smart network interface controller (smartnic) buffers

The technology disclosed relates to inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor and a second reconfigurable processor. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second reconfigurable processor using one or more SmartNIC buffers.

Inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers

The technology disclosed relates to runtime execution of configuration files on reconfigurable processors with varying configuration granularity. In particular, the technology disclosed relates to a runtime logic that is configured to receive a set of configuration files for an application, and load and execute a first subset of configuration files in the set of configuration files and associated application data on a first reconfigurable processor. The first reconfigurable processor has a first level of configurable granularity. The runtime logic is further configured to load and execute a second subset of configuration files in the set of configuration files and associated application data on a second reconfigurable processor. The second reconfigurable processor has a second level of configurable granularity that is different from the first level of configurable granularity.

Runtime execution of configuration files on reconfigurable processors with varying configuration granularity

A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, to generate multiple samples for a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

Adapative receiver with pre-cursor cancelation

The technology disclosed relates to buffer-based inter-node streaming of configuration data over a network fabric. In particular, the technology disclosed relates to a runtime processor configured to load and execute a first subset of configuration files in a set of configuration files on a first reconfigurable processor operatively coupled to a first processing node, load and execute a second subset of configuration files in the set of configuration files on a second reconfigurable processor operatively coupled to a second processing node, and use a first plurality of buffers operatively coupled to the first processing node, and a second plurality of buffers operatively coupled to the second processing node to stream data between the first reconfigurable processor and the second reconfigurable processor to load and execute the first subset of configuration files and the second subset of configuration files.

Inter-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS)

A data processing system comprises a plurality of reconfigurable processors including a first reconfigurable processor and additional reconfigurable processors, a plurality of buffers in a shared memory accessible to the first reconfigurable processor and the additional reconfigurable processors, and runtime logic configured to execute one or more configuration files for applications using the first reconfigurable processor and the additional reconfigurable processors. Execution of the configuration files includes receiving data from the first reconfigurable processor and providing the data to at least one of the additional reconfigurable processors, and receiving data from the at least one of the additional reconfigurable processors and providing the data to the first reconfigurable processor.

Intra-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS)

A method and apparatus for correcting baseline wander is disclosed. The method and apparatus may include generating filtered signals by filtering input signals using a filter circuit. An equalizer circuit using the filtered signals may generate output signals. Feedback networks may be configured to couple a respective output signal to a corresponding filtered signal.

Baseline wander correction in AC coupled communication links using equalizer with active feedback

A reference generator for use with serial link data communication is disclosed. Broadly speaking, a decision circuit may perform a comparison between a particular data symbol included in a serial data stream and a difference between a voltage level of a first signal and a voltage level of a second signal, and generate an output data value based on a result of the comparison. A reference generator circuit may selectively sink a first current value from either the first signal or the second signal based upon another output data value generated from another data symbol included in the serial data stream that was received prior to the particular data symbol.

Fast-settling voltage reference generator for SERDES applications

A method and an apparatus for correcting baseline wander is disclosed. The method and apparatus may include receiving a serial data stream that encodes a plurality of data symbols, and determining an average magnitude of a first data value included in one or more data symbols of a subset of the plurality of data symbols, and an average magnitude of a second value included in the one of more data symbols of the subset of the plurality of data symbols. A common mode operating point of an equalizer circuit may be adjusted using the average magnitude of the first data value and the average magnitude of the second data value.

Baseline wander correction using zero and one mismatch adaptation

A social media enrichment framework is described herein. In one or more embodiments, the framework is configured to store a set of interface endpoints for accessing different sources of analytic metadata. The framework further stores a set of mappings between social media object types and interface endpoints. Responsive to receiving a social media object having a particular social media object type, the framework identifies, within the set of mappings, a mapping between the particular social media object type and at least one interface endpoint in the set of interface endpoints. The framework then obtains, from one or more sources using the at least one interface endpoint, a set of one or more metrics relevant to the social media object and stores the set of one or more metrics in association with the social media object.

Social media enrichment framework

Growing community of inventors

San Diego, CA, United States of America

Dawei Huang