Beken Corporation

Gm Global Technolgoy Operations, Inc.

Beken Corp Shenzhen

Dawei Guo

Jiazhou Liu

Ronghui Kong

Desheng Hu

Pengfei Zhang

Caogang Yu

Donghui Gao

Hwasup Lee

Yanfeng Wang

Peng Han

Yunfeng Zhao

Weifeng Wang

Yunfeng Chen

Yangeng Wang

Jianqin Zheng

Vehicle liftgate

Vehicle hood

Vehicle fender

A PVT calculation device includes a memory; and one or more processors in communication with the memory configured to perform operations including: receiving observations and ephemerides from satellites to obtain PVT data of the satellites and predicted PVT results of the receiver; setting up observation functions respectively corresponding to the satellites; calculating by a least square solution first estimated PVT results of the receiver based on the observation functions; iteratively eliminating by a Random-Sampling Iterative Kalman Filter (RSIKF) algorithm fault observation functions from the observation functions in an inner cluster until no fault observation functions detected in the inner cluster; calculating by the RSIKF algorithm a second estimated PVT results of the receiver using the observation functions in the inner cluster; and outputting final estimated PVT results of the receiver. The PVT calculation device may calculate the PVT results of the receiver with improved accuracy and stability.

Apparatus and method of calculating position-velocity-time results of receiver

A Weil code generator and a method of generating Weil codes with a Weil code length (N) are provided. The Weil code generator includes a plurality of parallel channels (), a multi-channel read arbiter (), and two parallel Legendre ROMs (), which are connected in series. A channel of the plurality of channels stores a current Weil code to demodulate signals from a satellite. The multi-channel read arbiter () may determine a win channel from the plurality of channels. The two Legendre ROMs () respectively store a first and a second Legendre sequences (LS1, LS2) each having a Legendre sequence length (2N) being double the Weil code length (N). The Weil code generator may generate Weil codes efficiently.

Apparatus and method of generating Weil codes

A bias circuit includes a digital-to-analog converter configured to receive a digital input and output an analog signal; an integrator coupled to a first node that is coupled to the digital-to-analog converter and an amplifier, and coupled to a second node that is coupled to a positive input port of a first comparator and a negative input port of a second comparator; the digital signal processor coupled to an output port of the first comparator and an output port of the second comparator, and coupled to an input port of the digital-to-analog converter.

Signal processing bias circuit for microphone

A method and a system of calibrating a DC offset voltage on a resistor load are provided. The system may include a first operational amplifier, a second operational amplifier, a comparator, a digital signal processor, and a digital to analog convertor. At a calibration mode, under control of the digital signal processor, the system may utilize open-loop high gain characteristics of the first operational amplifier and the comparator to automatically detect and calibrate the DC offset voltage. At an operation mode, the system may automatically compensate the DC offset voltage based on the calibration of the DC offset voltage. In this way, the system and the method can automatically detect, calibrate, and compensate the DC offset voltage with reduced cost and technical complexity.

Calibration of audio power amplifier DC offset

A low pass filter embedded digital-to-analog converter including a first switch coupled to a first node that is coupled to a fourth switch and a first capacitor, a second switch coupled to a second node that is coupled to the first capacitor and a third switch, a negative input of a first operational amplifier coupled to a third node that is coupled to the third switch and a second capacitor, and an output port of the first operational amplifier coupled to a fourth node that is coupled to the second capacitor and the fourth switch.

Low pass filter embedded digital-to-analog converter

A frequency synthesizer, comprises a phase frequency detector to receive a frequency signal and a reference clock, and to output a phase difference according to a phase difference and a frequency difference between the frequency signal and the reference clock; a charge pump to generate a current according to the phase difference; a loop filter to generate a first voltage signal based on the current; a N-path filter each comprising a switch, a path filter and to generate N paths of filtered voltages based on the first voltage; a voltage control oscillator to generate a second voltage signal based on a sum of the N paths of filtered voltages; a frequency divider to generate the frequency signal based on the second voltage signal and a variable frequency dividing ratio; and a Sigma-Delta Modulator to generate the variable frequency dividing ratio based on a digital representation of a frequency fractional value and the reference clock.

Frequency synthesizer and method of operating the same

A method and a circuit for exciting a crystal oscillation circuit are disclosed herein. The crystal oscillation circuit comprising: charging, with a charging circuit, a voltage-controlled oscillator; providing, with the voltage-controlled oscillator, an exciting signal; blocking, with a direct current blocking capacitor, direct current from the voltage-controlled oscillator to the crystal oscillation circuit; and exciting, with the exciting signal, the crystal oscillation circuit. The circuit for exciting a crystal oscillation circuit, comprising: a charging circuit; a voltage-controlled oscillator coupled to the charging circuit and configured to provide an exciting signal to the crystal oscillation circuit; and a direct current blocking capacitor connected between the voltage-controlled oscillator and the crystal oscillation circuit and configured to block direct current from the voltage-controlled oscillator.

Method and circuit for exciting a crystal oscillation circuit

A fractional-N frequency synthesizer comprising a multi-phase generator, a multi-path error phase generator; a current combiner; a loop filter connected to the current combiner; an oscillator () connected to the loop filter; a frequency divider (); a SDM connected to both the frequency divider and the multi-phase generator, to generate variable division ratio.

Fractional-N frequency synthesizer and method thereof

An embodiment discloses an operational amplifier comprising: an input stage; an output stage communicatively coupled to the input stage, wherein the output stage further comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first current source, a fifth transistor, a sixth transistor and a second current source, wherein a second node of the first transistor is connected to the input stage (vin), a third node of the first transistor is connected to a third node of the fourth transistor, ground (gnd), a third node of the fifth transistor and a third node of the third transistor, a first node of the first transistor is connected to a first node of the first current source, a second node of the sixth transistor and a second node of the second transistor.

Output stage of operational amplifier and method in the operational amplifier

A voltage-to-current converting circuit, comprising: a direct current (DC) bias circuit, a first DC-blocking circuit, a second DC-blocking circuit, a first differential input pair and a second differential input pair; wherein the DC bias circuit is connected to the first and second DC-blocking circuits and configured to provide a bias voltage to the first and the second differential input pairs; wherein the first DC-blocking circuit is connected between the DC bias circuit and the first and second differential input pair and the second DC-blocking circuit is connected between the DC bias circuit and the first and second differential input pair; and wherein the first differential circuit is connected to the second differential circuit via two resistors.

Radio frequency voltage-to-current converting circuit and method

A switching unit comprises a COordinate Rotation DIgital Computer (CORDIC) unit configured to estimate a maximum phase difference between a phase of the GFSK modulated signal to be switched and a phase of the QPSK modulated signal after switch; a timing unit communicatively coupled to the CORDIC unit and configured to generate adaptive steps according to a switch time and the estimated maximum phase difference, wherein the CORDIC is further configured to generated an adjusted GFSK modulated signal by adjusting a phase of the GFSK modulated signal to be switched according to the estimated maximum phase difference and the adaptive steps.

Transmitter for transmitting packets and method thereof

A method for suppressing POP noise in an audio operation amplifier, comprising: connecting a first resistor and a second resistor in series at an output stage of the audio operation amplifier by turning on a first switch and a second switch; generating, with a ramp generator, a ramp voltage after an audio signal is input into the audio operation amplifier, wherein the ramp voltage varies from zero to a first value; generating, with an voltage generator, a second voltage, wherein a third switch is turned on and a fourth switch is turned off when the ramp voltage reaches the second value; short-circuiting the first and second resistors by turning off the first and second switches; and outputting, with the audio operation amplifier, an amplified audio signal.

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Shanghai, China

Dawei Guo