Xilinx, Inc.

Davis Moore

Chirag Ravishankar

Steven P Young

Brian C Gaide

Dinesh D Gaitonde

Eric F Dellinger

Jay T Young

Aashish Tripathi

Abhishek Kumar Jain

Maithilee Rajendra Kulkarni

Ashit Debnath

A 3D device includes a first semiconductor chip and a second semiconductor chip stacked vertically. The first semiconductor chip includes a first plurality of tiles. The second semiconductor chip includes a second plurality of tiles. A bus electrically couples each of the first plurality of tiles to a corresponding one of the second plurality of tiles based on assignments of the first plurality of tiles and the second plurality of tiles to tile-to-tile pairs that define a minimized sum of bus delays among each possible tile-to-tile pairs. In each tile-to-tile pair, a net electrically couples each of a first plurality of pins to a corresponding one of a second plurality of pins based on assignments of the first plurality of pins to the second plurality of pins that define a minimized sum of net delays among each possible pin-to-pin pairs.

3D stacked device having improved data flow

Circuit pin constraints input to a design tool specify respective sets of circuit pins belonging to circuit blocks, and input interface pin constraints specify respective sets of interface pins belonging to instances of an interface circuit. The design tool generates pin solutions, and each pin solution includes pin assignments of the circuit pins to the interface pins. The design tool applies an objective function to the pin solutions and selects one pin solution that satisfies the objective function. The design tool then specifies in a circuit design, connections between the circuit pins and the interface pins according to the selected pin solution.

Method and system for making pin-to-pin signal connections

A system comprises a pair of configurable logic blocks (CLBs) placed adjacent to each other wherein each of the CLBs includes a plurality of configurable logic elements. A plurality sets of inodes are configured to accept signals to and/or from the CLBs, wherein a first set of inodes is positioned to the left of the adjacent CLBs and a second set of inodes is positioned to the right of the adjacent CLBs. A plurality of bnodes are embedded in the middle of the adjacent CLBs, wherein each bnode is configured to establish a first connection between the bnode and one of the first set of inodes on the left of the CLBs and a second connection between the bnode and one of the second set of inodes on the right of the CLBs. Both the first and second routing connections are localized within the pair of adjacent CLBs.

Configurable logic block (CLB) internal routing architecture for enhanced local routing and clocking improvements

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Davis Moore