Infineon Technologies Austria Ag

Davide Respigo

Massimo Grasso

Sergio Morini

Wolfgang Frank

Christian Locatelli

Diego Raffo

Amedeo Paganini

Andrea Luigi Francesco Mariconti

A gate driver includes a high-side region that operates in a first voltage domain, a low-side region that operations in a second voltage domain lower than the first voltage domain, a termination region interposed between the high-side region and the low-side region and configured to isolate the first voltage domain from the second voltage domain, a high-side gate driver disposed in the high-side region and configured to drive a high-side power transistor, a low-side gate driver disposed in the low-side region and configured to drive a low-side power transistor, and a plurality of termination diodes disposed in the termination region and configured to transmit information bits between the high-side region and the low-side region, where each of the plurality of termination diodes includes an anode coupled to the low-side region and a cathode coupled to the high-side region.

Low power cycle to cycle bit transfer in gate drivers

A gate driver circuit for driving a power switch includes a gate driver having a first input for receiving an input signal and an output coupled to the power switch, the gate driver providing a primary gate current and an auxiliary gate current, and a differential voltage sensor having a first input for receiving the input signal, a second input coupled to a power supply voltage, a third input coupled to a terminal of the power switch, and an output coupled to a second input of the gate driver.

Adaptive multi-level gate driver

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Pavia, Italy

Davide Respigo