Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics (shenzhen) R&d Co. Ltd.

Davide Luigi Brambilla

Edoardo Botti

Giovanni Capodivacca

Daniela Nebuloni

Sergio Lecce

Fabrizio Stefani

Cristiano Meroni

Giorgio Rossi

Danilo Ranieri

Mauro Cleris

Tommaso Barbieri

Paolo Ferrari

Franco Maloberti

Hong Wu Lin

Mei Yang

Guido Brasca

Edoardo Bonizzoni

Francesco Stilgenbauer

Luca Celant

Paolo Cacciagrano

QiYu Liu

Fabio Chelli

Arunkumar Salimath

Shuming Tong

In an embodiment, an amplifier circuit includes a second stage that includes a first switch circuit including first and second terminals, a plurality of resistive elements coupled between the first and second terminals of the first switch circuit, and a plurality of switches configured to control an equivalent resistance between the first and second terminals of the first switch circuit. During play mode, the second stage has a gain between the input of the second stage and the output of the second stage of a first value. During a transition from mute mode to play mode, the amplifier circuit is configured to progressively increase the gain of the second stage from a second value to the first value. During a transition from play mode to mute mode, the amplifier circuit is configured to progressively decrease the gain of the second stage from the first value to the second value.

Play mute circuit and method

An integrated circuit includes a die that includes a circuit configured to generate a PWM signal in response to a first clock signal, and a first set of pads configured to provide amplified PWM signals to external filters. An amplifier stage is configured to provide the amplified PWM signals. The die includes two pads configured to be coupled to an external inductor, and a second set of pads configured to provide regulated voltages. An electronic converter circuit is configured to generate the regulated voltages to supply the amplifier stage. The electronic converter circuit includes a control circuit configured to drive electronic switches in response to a second clock signal to regulate the regulated voltages to a respective target value. The die includes a control block to synchronize the switching activity of the electronic switches with the switching activity of the amplifier stage.

Integrated circuit and related audio amplifier

A circuit includes a field effect transistor having a gate driven via a drive signal. The field effect transistor has a drain-source voltage drop indicative of the intensity of a current flowing in the current path through the field effect transistor. The circuit also includes a pair of sensing transistors that include a first sensing field effect transistor arranged with its drain and gate coupled with the drain and the gate of the field effect transistor, respectively, and a second sensing field effect transistor having a gate configured for receiving a replica of the drive signal. The second sensing field effect transistor is arranged with its current path in series with the current path of the first sensing field effect transistor. A sensing signal at a sensing node is indicative of the current intensity flowing in the current path of the field effect transistor.

Current sensing circuit and method

A converter includes a first switch coupled between a first input terminal and a first terminal of an inductor, and a second switch coupled between a second terminal of the inductor and a second input terminal. A third switch is coupled between the second terminal of the inductor and a first output terminal, and a fourth switch is coupled between the first terminal of the inductor and a second output terminal. A capacitor is coupled between the first and second output terminals. A control circuit monitors a regulated voltage between the first and second output terminals. During a charge phase, the first and second switches are closed to charge the inductor. During a discharge phase, the third and fourth switches are closed to charge the capacitor and increase the regulated voltage.

Electronic converter, related audio system, integrated circuit and method of operating an electronic converter

A common mode control circuit reduces abrupt voltage changes at the outputs of a pair of amplifiers which, in turn, reduces EMI and distortions that occur when the correlation between the signals fed to the four channels of an audio system diminishes. The common mode control circuit generates for each amplifier a reference potential that is a saturated replica of the respective differential input signal of the amplifier that saturates when the amplifier switches to a bridge configuration.

Method of preventing abrupt voltage changes at the outputs of a pair of amplifiers and control circuit for a pair of amplifiers self-configuring in a bridge configuration

A method of assessing the offset on the output nodes of an amplifying channel includes generating a logic signal for signaling the existence of an offset having a level exceeding a window of permitted levels symmetric about the zero level. The window is defined by a negative limit value and by a positive limit value. The method includes establishing an interval or phase of detection by applying to an input of a detection circuit a timing pulse with a certain frequency, sensing the rising edge of the timing pulse and setting a bistable circuit, and comparing the signal on the output nodes of the amplifiers channel with the window of permitted values. The bistable circuit is reset upon the occurrence, after the initial setting, of an output signal amplitude within the window of permitted values. Failure of the bistable circuit to reset before the end of the detection phase signals an excessive offset.

Method of anomalous offset detection and a corresponding circuit

An amplifier having an input; an output supplying an output signal, and a feedback network connected between the input and the output, and a distortion detection circuit. The feedback network includes a first and a second feedback element arranged in series and forming an intermediate node supplying an intermediate signal in phase with the output signal in absence of distortion, and in phase-opposition with the output signal in presence of distortion. The distortion detection circuit includes a phase-comparating circuit which detects the phase of the output signal and of the intermediate signal, and generates a distortion-indicative signal, when the intermediate signal is in phase opposition with respect to the output signal.

Circuit for detecting distortion in an amplifier, in particular an audio amplifier

A method of voltage driving a load using a controlled current includes providing a negative feedback of an output current, measuring the output current on a collector of an output transistor of an output stage, comparing the measured output current with an input current to define a current difference, and providing the current difference at a base of the output transistor to provide the voltage driving.

Controlled current, voltage mode driving stage

An integrated circuit for producing a small slope voltage ramp includes a circuit for generating a periodic triangular current signal, and a circuit for generating, at the beginning of each period of the triangular signal, a pulse of a certain duration which is much smaller than the period of the triangular signal. A control loop is input at a node with the triangular current signal and produces the desired slow voltage ramp on the output node. The control loop includes a first hold circuit coupled to the input node via a first switch controlled by the pulse, and a transconductance operational amplifier, whose inputs are respectively coupled to the input node and to the output node. Also, the control loop includes a second hold circuit coupled to the output of the operational transconductance amplifier via a second switch controlled in a complementary manner with respect to the first switch. A resistor of a much smaller value than the ratio between the period of the triangular signal and the capacitance of the storage capacitor of the first hold circuit is connected between the output of the second hold circuit and the input node.

Integrated generator of a slow voltage ramp

A circuit for ensuring a complete saturation of both operational amplifiers of a single-input bridge amplifier is provided. A voltage divider is connected between the inverting inputs of the two amplifiers and a saturation current signal is injected on the intermediate node of the voltage divider. Such a saturation current signal is obtained through dedicated sensing devices of the state of saturation reached by the transistors of the output stages of both amplifiers of the single-input bridge amplifier.

Circuit for ensuring full saturation of amplifiers of a single input configured bridge amplifier

The anti-pop circuit includes a unity gain buffer with an input coupled to the source of the reference voltage and an output coupled to the input of the amplifier to accelerate the charging of the input coupling capacitor of the amplifier at every turn-on. The capacitor-charging buffer is automatically disabled before the turning-on of the amplifier. The charging buffer may be enabled at start up by generating an impulse of a pre-established duration at the turn-on instant by a monostable circuit or by disabling it upon verifying the decaying to zero of the charging of current of the input coupling capacitor. The circuit eliminates the popping noise at the turn-on without an excessive delay of the turning-on of the amplifier.

Anti-pop circuit for AC amplifiers

A current generator circuit with controllable frequency response has at least one current mirror formed of MOS transistors, being powered through a terminal held at a constant voltage, having an input leg through which a reference current (I1) is driven by a first current generator (G1), and having an output leg for generating, on an output terminal (OUT) of the mirror, a mirrored current (I.sub.out) which is proportional to the reference current (I1). The input leg includes at least a first transistor (M1) which is diode-connected and has a control terminal (Ga1) coupled to a corresponding terminal (Ga2) of a second transistor (M2) included in the output leg. In accordance with the invention, the mirror circuit also has an impedance matching circuit connected across the control terminals (Ga1 and Ga2) of the first and second transistors and configured to hold the same voltage value at both terminals (Ga1 and Ga2). The impedance matching circuit has an adjustable output impedance, specifically lower in value than the value to be had without this circuit. It functions to regulate the impedance on the control node (Ga2) of the second transistor (M2). The invention is equally applicable to N-channel and P-channel MOS transistors. Advantageously, the reference current can be varied by an external signal which is a function of the output signal, to provide feedback regulating features.

Current generator circuit having a wide frequency response

A semiconductor circuit includes a semiconductor layer having a surface and a monolithic output stage formed in the semiconductor layer. The monolithic output stage extends to the surface of the semiconductor layer and has a periphery within the semiconductor layer, an output terminal, and a supply terminal. A barrier well is formed in the semiconductor layer and adjacent to at least a portion of the periphery of the monolithic output stage. The barrier well extends to the surface of the semiconductor layer and has a first conductivity. A diode having first and second diode regions is disposed in the semiconductor layer. The first diode region is coupled to the supply terminal. The diode is operable to prevent current flow from the barrier well to the supply terminal when the voltage between the supply and output terminals has a first polarity.

Semiconductor device having improved latch-up protection

A current generator circuit with controllable frequency response has at least one current mirror formed of MOS transistors, being powered through a terminal held at a constant voltage, having an input leg through which a reference current (I1) is driven by a first current generator (G1), and having an output leg for generating, on an output terminal (OUT) of the mirror, a mirrored current (I.sub.out) which is proportional to the reference current (I1). The input leg includes at least a first transistor (M1) which is diode-connected and has a control terminal (Ga1) coupled to a corresponding terminal (Ga2) of a second transistor (M2) included in the output leg by an impedance matching circuit configured to hold the same voltage value at both terminals (Ga1 and Ga2). The impedance matching circuit has an adjustable output impedance, specifically lower in value than the value to be had without this circuit. It functions to regulate the impedance on the control node (Ga2) of the second transistor (M2). The invention is equally applicable to N-channel and P-channel MOS transistors. Advantageously, the reference current can be varied by an external signal which is a function of the output signal, to provide feedback regulating features.

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Segrate, Italy

Davide Luigi Brambilla