Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics Gmbh

Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno

Co.ri.m.me. Consorzio Per La Ricerca Sulla Microelettronica Nel

Co.ri.m.me Consorzio Per La Sulla Microelectronica Nel Mezzogiorno

Davide Giuseppe Patti

Salvatore Leonardi

Marco Morelli

Natale Aiello

Antonio Giuseppe Grimaldi

Mario Antonio Aleo

Salvatore Giuseppe Privitera

Giuseppina Valvo

Piero Fallica

Mario Paparo

Delfo Nunziato Sanfilippo

Fabrizio Fausto Renzo Toia

Antonino Torres

Simone Dario Mariani

Giuseppe Barillaro

Marco Sambi

Salvatore Scaccianoce

Gianleonardo Grasso

Lorenzo Maurizio Selgi

Daria Puccia

Vincenzo Sciacca

DelfoNunziato Sanfilippo

Giuditta Settanni

Sergio Palara

Salvatore Coffa

Domenico Rossi

Agatino Minotti

Manuela La Rosa

Mario Giovanni Scurati

Cesare Ronsisvalle

Valeria Cinnera Martino

Angelo Pinto

Elisabetta Pizzi

Dario Sutera

Giuseppe Grasso

Manuela Larosa

Francesco Priolo

Cirino Rapisarda

Sebastiano Aparo

Giorgia Franzo

Vittorio Privitera

Myung Sung Kim

Pietro Lizzio

Monica Miccichè

Salvatore Liotta

Angela Longhitano

Alessandro Mascali

A process is proposed for manufacturing an integrated device having at least one MOS transistor integrated on a die of semiconductor material. The process includes forming one or more gate trenches with corresponding field plates and gate regions. A body region is formed by implanting dopants selectively along one or more implantation directions that are tilted with respect to a front surface of the die. Moreover, a corresponding integrated device and a system comprising this integrated device are proposed.

Split-gate trench MOS transistor with self-alignment of gate and body regions

A vertical conduction electronic power device includes a body delimited by a first and a second surface and having an epitaxial layer of semiconductor material, and a substrate. The epitaxial layer is delimited by the first surface of the body and the substrate is delimited by the second surface of the body. The epitaxial layer houses at least a first and a second conduction region having a first type of doping and a plurality of insulated-gate regions, which extend within the epitaxial layer. The substrate has at least one silicide region, which extends starting from the second surface of the body towards the epitaxial layer.

Vertical conduction electronic power device having a reduced on resistance and manufacturing process thereof

A field effect transistor has a semiconductor layer with a top surface extending in a horizontal plane, and an active area defined in which are trench gate regions, which extend in depth with respect to the top surface and have an insulating coating layer and a conductive inner layer, and source regions, adjacent to the trench gate regions so as to form a conductive channel extending vertically. The trench gate regions have a plurality of first gate regions, which extend in length in the form of stripes through the active area along a first direction of the horizontal plane, and moreover a plurality of second gate regions, which extend in length in the form of stripes through the same active area along a second direction of the horizontal plane, orthogonal to, and crossing, the first gate regions. In particular, the first gate regions and second gate regions cross in the active area, joining with a non-zero curvature radius.

Trench-gate field effect transistor with improved electrical performances and corresponding manufacturing process

A semiconductor die includes a structural body that has a power region and a peripheral region surrounding the power region. At least one power device is positioned in the power region. Trench-insulation means extend in the structural body starting from the front side towards the back side along a first direction, adapted to hinder conduction of heat from the power region towards the peripheral region along a second direction orthogonal to the first direction. The trench-insulation means have an extension, in the second direction, greater than the thickness of the structural body along the first direction.

Semiconductor die with improved thermal insulation between a power portion and a peripheral portion, method of manufacturing, and package housing the die

An integrated device includes at least one MOS transistor having a plurality of cells. In each of one or more of the cells a disabling structure is provided. The disabling structure is configured to be in a non-conductive condition when the MOS transistor is switched on in response to a control voltage comprised between a threshold voltage of the MOS transistor and an intervention voltage of the disabling structure, or to be in a conductive condition otherwise. A system comprising at least one integrated device as above is also proposed. Moreover, a corresponding process for manufacturing this integrated device is proposed.

Integrated MOS transistor with selective disabling of cells thereof

The power device is formed by a D-mode HEMT and by a MOSFET in cascade to each other and integrated in a chip having a base body and a heterostructure layer on the base body. The D-mode HEMT includes a channel area formed in the heterostructure layer; the MOSFET includes a first and a second conduction region formed in the base body, and an insulated-gate region formed in the heterostructure layer, laterally and electrically insulated from the D-mode HEMT. A first metal region extends through the heterostructure layer, laterally to the channel area and in electrical contact with the channel area and the first conduction region.

HEMT power device operating in enhancement mode and manufacturing process thereof

Power MOS device, in which a power MOS transistor has a drain terminal that is coupled to a power supply node, a gate terminal that is coupled to a drive node and a source terminal that is coupled to a load node. A detection MOS transistor has a drain terminal that is coupled to a detection node, a gate terminal that is coupled to the drive node and a source terminal that is coupled to the load node. A detection resistor has a first terminal coupled to the power supply node and a second terminal coupled to the detection node.

Power MOS device having an integrated current sensor and manufacturing process thereof

In various embodiments, the present disclosure provides capacitors and methods of forming capacitors. In one embodiment, a capacitor includes a substrate, a first electrode on the substrate, a second electrode, and a first dielectric layer. A portion of the first electrode is exposed in a contact region. The first dielectric layer includes a first dielectric region between the first electrode and the second electrode, and a second dielectric region between the first dielectric region and the contact region. The second dielectric region is contiguous to the first dielectric region, and a surface of the second dielectric region defines a surface path between the first electrode and the contact region. The second dielectric region has a plurality of grooves that increase a spatial extension of said surface path.

High-voltage capacitor, system including the capacitor and method for manufacturing the capacitor

Embodiments are directed to high electron mobility transistor (HEMT) devices and methods. One such HEMT device includes a substrate having a first surface, and first and second heterostructures on the substrate and facing each other. Each of the first and second heterostructures includes a first semiconductor layer on the first surface of the substrate, a second semiconductor layer on the first surface of the substrate, and a two-dimensional electrode gas (2DEG) layer between the first and second semiconductor layers. A doped semiconductor layer is disposed between the first and second heterostructures, and a source contact is disposed on the first heterostructure and the second heterostructure.

High electron mobility transistor (HEMT) devices and methods

A technique to make silicon oxide regions from porous silicon and related semiconductor structures is disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.

Semiconductor structure with partially embedded insulation region and related method

Growing community of inventors

Mascalucia, Italy

Davide Giuseppe Patti