Intel Corporation

David Zimmerman

Raj K Ramanujan

Rajesh Sundaram

Glenn J Hinton

Darshan Kobla

Shekoufeh Qawami

Michael W Williams

Muthukumar Swaminathan

Kuljit Singh Bains

Mohan J Kumar

John B Halbert

Dimitrios Ziakas

Bassam N Coury

Vimal K Natarajan

Blaise B Fanning

Rajat Agarwal

Theodore Zale Schoenborn

Kai Cheng

Robert W Faber

Bruce Querbach

David G Ellis

Robert M Ellis

Camille C Raad

Taarinya Polepeddi

William K Lui

Liwei Ju

Joon-Sung Yang

Christopher W Hampson

Ifar Wan

Yulan Zhang

Jun Shi

Tak Ming Mak

Dennis W Brzezinski

Christopher J Nelson

Chris B Freeman

Francesc Guim Bernat

Aaron K Martin

Pete D Vogt

Derchang Kau

Robert S Chappell

John C Johnson

Rameshkumar G Illikkal

Rajesh S Parthasarathy

Pratik M Marolia

Dave B Minturn

Adrian C Moga

Wayne Alan Downer

Jay Joseph Nejedlo

Madhavan Parthasarathy

Larry O Smith

Rasika Subramanian

Ramasubramanian Rajamani

Scott J Cape

Ananth Sankaranarayanan

Suchit Subhaschandra

Derek B Feltham

Ramakrishna Mallela

Edward Weaver

Wayne A Downer

Examples described herein can be used to determine and suggest a computing resource allocation for a workload request made from an edge gateway. The computing resource allocation can be suggested using computing resources provided by an edge server cluster. Telemetry data and performance indicators of the workload request can be tracked and used to determine the computing resource allocation. Artificial intelligence (AI) and machine learning (ML) techniques can be used in connection with a neural network to accelerate determinations of suggested computing resource allocations based on hundreds to thousands (or more) of telemetry data in order to suggest a computing resource allocation. Suggestions made can be accepted or rejected by a resource allocation manager for the edge gateway and the edge server cluster.

Accelerated resource allocation techniques

Aspects of the embodiments are directed to systems, devices, and methods for accessing storage-as-memory. Embodiments include a microprocessor including a microprocessor system agent and a field programmable gate array (FPGA). The FPGA including an FPGA system agent to process memory access requests received from the microprocessor system agent across a communications link; a memory controller communicatively coupled to the system agent; and a high speed serial interface to link the system agent with a storage system. Embodiments can also include a storage device connected to the FPGA by the high speed serial interface.

Systems and methods for accessing storage-as-memory

A system and method are described for flushing a specified region of a memory side cache (MSC) within a multi-level memory hierarchy. For example, a computer system according to one embodiment comprises: a memory subsystem comprised of a non-volatile system memory and a volatile memory side cache (MSC) for caching portions of the non-volatile system memory; and a flush engine for flushing a specified region of the MSC to the non-volatile system memory in response to a deactivation condition associated with the specified region of the MSC.

Dynamic partial power down of memory-side cache in a 2-level memory hierarchy

A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as 'far memory.' Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as 'near memory.'

Apparatus and method for implementing a multi-level memory hierarchy

Devices, systems, and methods having increased efficiency selective writing to memory are disclosed and described. A memory controller, upon receiving a dirty data segment, performs a read-modify-write to retrieve a corresponding data line from memory, saves a copy of the data line, merges the dirty data segment into the appropriate location in the data line to create a modified data line, and generates a write mask from the modified data line and the copy of the data line.

Write data mask for power reduction

Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.

Adaptive configuration of non-volatile memory

A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.

Boundary scan chain for stacked memory

Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.

Self-repair logic for stacked memory architecture

A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

Interface for storage device access over memory bus

In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets.

Integrated circuit defect detection and repair

Growing community of inventors

El Dorado Hills, CA, United States of America

David Zimmerman