Taiwan Semiconductor Manufacturing Comp. Ltd.

David Yen

Kuoyuan (Peter) Hsu

Sung-Chieh Lin

Jiann-Tseng Huang

Wei-Li Liao

Hung-Wen Chen

Po-Hung Chen

Chih-Fu Chang

Tsai-Hsin Lai

Yao-Jen Tsai

Ching-Yun Chang

Chi-Hsu Chiu

Hung-Che Hsueh

Chih Mou Huang

Cheng-Hsu Wu

Eric Hu

Kevin Yen

Chih-Kang Chuang

Yee-Ren Wuang

Yuan-Jen Liao

Shih-Che Fang

A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also includes forming an NMOS transistor in the substrate and outside the DNW, and forming a reverse-biased diode. The method further includes forming an electrical path between a drain of the PMOS transistor and a gate structure of the NMOS transistor. The dissipation device is also connected to the electrical path.

Integrated circuit structure

Integrated circuit structure to resolve deep-well plasma charging problem and method of forming the same

During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.

A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on.

Electrical fuse memory

An embodiment is an integrated circuit (IC) structure. The structure comprises a deep n well in a substrate, a first pickup device in the deep n well, a first signal device in the deep n well, a dissipation device in the substrate, a second signal device in the substrate, a first electrical path between the first pickup device and the dissipation device, and a second electrical path between the first signal device and the second signal device. The dissipation device is outside of the deep n well, and the second signal device is outside of the deep n well. A highest point of the first electrical path is lower than a highest point of the second electrical path.

Integrated circuit structure and method of forming the same

The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a non-salicided polysilicon fuse. The non-salicided polysilicon fuse and a programming transistor form a one-time programmable (OTP) memory cell, which can be programmed with a low programming voltage.

Non-salicide polysilicon fuse

An input of a first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of a second inverter. An output of the second inverter is configured to serve as an output node. An input of a third inverter is coupled to an input of the first inverter. A gate of a first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as a level input node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node.

Voltage level shifter

Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row.

A memory cell includes a write access transistor coupled between a storage node and a write bit line, and active during a write cycle responsive to a voltage on a write word line; a read access transistor coupled between a read word line and a read bit line, and active during a read cycle responsive to a voltage at the storage node; and a storage capacitor coupled between the read word line and the storage node. Methods for operating the memory cell are also disclosed.

Circuit for high speed dynamic memory

A method for performing a synchronized order change in a manufacturing process is provided. An order is associated with an order number and a work in process (WIP) number, which identifies a physical lot corresponding to the order. The synchronized order change maintains a relationship between the order number and the WIP number while making the change. This avoids the need to scrap lots that are no longer associated with an order number and prevents holds from being placed on incorrect lots.

Method for processing order changes in a manufacturing system

An apparatus for attenuating physical damage to a substrate, along with an attendant method, comprises as a first component a base plate having defined therein a location for receiving a substrate cassette. The apparatus also comprises a substrate retainer movably attached to the base plate such that when the substrate cassette having a substrate contained therein is positioned on the base plate at the location for receiving the substrate cassette, and the substrate is subjected to a mechanical force, the substrate retainer moves such as to retain the substrate within the substrate cassette with a retaining force. Both the apparatus and the method are particularly applicable for attenuating damage to a substrate when spin-drying the substrate.

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Chu-Bak, Taiwan

David Yen