Solexel, Inc.

Tesla, Inc.

Ob Realty, LLC

Selexel, Inc.

Viamems Technologies, Inc.

David Xuan-Qi Wang

Mehrdad M Moslehi

Karl-Josef Kramer

Pawan Kapur

Sean M Seutter

Anthony Calcaterra

Somnath S Nag

Sam Tone Tor

George D Kamian

Takao Yonehara

Virendra V Rana

Jay Ashjaee

Emmanuel Van Kerschaver

Suketu Arun Parikh

Anand Deshpande

Michael Wingert

Joe Kramer

Thom Stalcup

Virenda V Rana

Yen-Sheng Su

Rafael Ricolcol

K-Josef Kramer

Gerry Olsen

Kamran Manteghi

An electrostatic device includes a top and a bottom silicon layer, around an insulating buried layer. A beam opening allows a beam of charged particles to travel through. The device is encapsulated in an insulating layer. One or more electrodes and ground planes are deposited on the insulating layer. These also cover the inside of the beam opening. Electrodes and ground planes are physically and electrically separated by micro-trenches and micro-undercuts that provide shadow areas when the conductive areas are deposited. Electrodes may be shaped as elongated islands and may include portions overhanging the top silicon layer, supported by electrode-anchors. Manufacturing starts from a single wafer including the top, buried, and bottom layers, or it starts from two separate silicon wafers. Manufacturing includes steps to form the top and bottom beam openings and microstructures, to encapsulate the device in an insulating layer, and to deposit electrodes and ground areas.

Electrostatic devices to influence beams of charged particles

Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects are described. The method comprises depositing an interdigitated pattern of base electrodes and emitter electrodes on a backside surface of a semiconductor substrate, forming electrically conductive emitter plugs and base plugs on the interdigitated pattern, and attaching a backplane having a second interdigitated pattern of base electrodes and emitter electrodes at the conductive emitter and base plugs to form electrical interconnects.

Backplane reinforcement and interconnects for solar cells

In one embodiment, there is provided a carrier comprising a top semiconductor layer having isolated positive electrode regions and isolated negative electrode regions separated by a frontside trench through the top semiconductor layer extending at least to an underlying insulating layer positioned between the top semiconductor layer and a bottom semiconductor layer. A dielectric layer covers the top exposed surfaces of the carrier. Backside trenches through the bottom semiconductor layer extending at least to the insulating layer form isolated backside regions corresponding to the frontside positive and negative electrode regions. Backside contacts positioned on the bottom semiconductor layer and coupled to the positive and negative electrode regions allow for the electric charging of the frontside electrode regions.

Bipolar mobile electrostatic carriers for wafer processing

Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects as well as Fabrication methods and structures for forming thin film back contact solar cells are described.

High-efficiency solar photovoltaic cells and modules using thin crystalline semiconductor absorbers

A three-dimensional thin-film semiconductor substrate with selective through-holes is provided. The substrate having an inverted pyramidal structure comprising selectively formed through-holes positioned between the front and back lateral surface planes of the semiconductor substrate to form a partially transparent three-dimensional thin-film semiconductor substrate.

Three-dimensional thin-film semiconductor substrate with through-holes and methods of manufacturing

A semiconductor template having a top surface aligned along a (100) crystallographic orientation plane and an inverted pyramidal cavity defined by a plurality of walls aligned along a (111) crystallographic orientation plane. A method for manufacturing a semiconductor template by selectively removing silicon material from a silicon template to form a top surface aligned along a (100) crystallographic plane of the silicon template and a plurality of walls defining an inverted pyramidal cavity each aligned along a (111) crystallographic plane of the silicon template.

Three-dimensional semiconductor template for making high efficiency solar cells

An apparatus for forming porous silicon layers on at least two surfaces of a plurality of silicon templates in a batch electrochemical anodic etch process is provided. The apparatus comprises a plurality of edge-sealing template mounts operable to prevent formation of porous silicon at the edges of a plurality of templates. An electrolyte is disposed among the plurality of templates. The apparatus further comprises a power supply operable to switch polarity, change current intensity, and control etching time to produce the porous silicon layers.

Apparatus for forming porous silicon layers on at least two surfaces of a plurality of silicon templates

According to one embodiment, a releasing apparatus for separating a semiconductor substrate from a semiconductor template, the releasing apparatus having an enclosed pressure chamber having at least one gas inlet and at least one gas outlet. A top vacuum chuck for securing a released semiconductor substrate or semiconductor template in the enclosed pressure chamber. A bottom vacuum chuck for securing an attached semiconductor substrate and semiconductor template in the enclosed pressure chamber. A gap between the attached semiconductor substrate and semiconductor template and the top vacuum chuck allowing gas flowing through the gap to generate lifting forces on the attached semiconductor substrate and semiconductor template.

Releasing apparatus for separating a semiconductor substrate from a semiconductor template

A method is provided for fabricating a semiconductor substrate by forming a porous semiconductor layer conformally on a semiconductor template and then forming a semiconductor substrate conformally on the porous semiconductor layer. An inner trench having a depth less than the thickness of the semiconductor substrate is formed on the semiconductor substrate. An outer trench providing access to the porous semiconductor layer is formed on the semiconductor substrate and is positioned between the inner trench and the edge of the semiconductor substrate. The semiconductor substrate is then released from the semiconductor template.

Trench formation method for releasing a substrate from a semiconductor template

Back contact back junction solar cell and methods for manufacturing are provided. The back contact back junction solar cell comprises a substrate having a light capturing frontside surface with a passivation layer, a doped base region, and a doped backside emitter region with a polarity opposite the doped base region. A backside passivation layer and patterned reflective layer on the emitter form a light trapping backside mirror. An interdigitated metallization pattern is positioned on the backside of the solar cell and a permanent reinforcement provides support to the cell.

High-efficiency photovoltaic back-contact solar cell structures and manufacturing methods

Methods here disclosed provide for selectively coating three-dimensional features on a substrate while avoiding liquid coating material wicking into micro cavities on the substrates. The steps include depositing a semiconductor layer on a sacrificial layer formed on a template and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating three-dimensional features on the substrate using a liquid coating step for applying a liquid coating material to a pre-determined surface of the three-dimensional features on the substrate.

Growing community of inventors

Fremont, CA, United States of America

David Xuan-Qi Wang