Arm Limited

Advanced Risc Machines Limited

David William Howard

David Walter Flynn

James Edward Myers

John Philip Biggs

Shidhartha Das

Bal S Sandhu

David Michael Bull

Robert Campbell Aitken

Sachin Satish Idgunji

Parameshwarappa Anand Kumar Savanth

Dhrumil Gandhi

Carsten Tradowsky

Simon Michael Ford

A circuit comprises an array of programmable memory elements fabricated on a substrate, each memory element having one or more processable regions which, when processed by an external process in which a material is applied to at least partially cover one or more of the regions, are configured to program that memory element to one of multiple states; a first set of control lines connected to the array of memory elements, by which the contents of each individual memory element are capable of being accessed by control signals applied to a respective combination of at least two control lines in the first set of control lines; and an array of second circuit elements, different to the memory elements, each connected to a control line of the first set of control lines and to another control line of a second set of control lines, different to the first set of control lines, so as to provide access to second circuit elements in the array.

Array of programmable memory elements with an array of second circuit elements

An electronic devicehas circuitrywhich operates in a first voltage domainsupplied with a first voltage level VDDand a reference voltage level. A voltage regulatorgenerates the first voltage level VDDfrom a second voltage level VDDhigher than the first voltage level VDD. At least one power gateis provided for selectively coupling the circuitryto one of the first voltage level VDDor the reference level. The control signalfor the power gateis generated in a second voltage domain supplied with a higher voltage level VDDor VDDderived from the second voltage level VDDsupplied to the voltage regulator. Hence, an existing high voltage source within the devicecan be reused for applying a boosted voltage to power gates to improve efficiency of power gating.

Power gating in an electronic device

An integrated circuit and method are provided for controlling variation in the voltage output from on-chip voltage generation circuitry. The integrated circuit comprises voltage generation circuitry configured to operate from a supplied input voltage and to generate at an output node an on-chip voltage supply different to the supplied input voltage. A circuit block is then arranged to receive the on-chip voltage supply generated by the voltage generation circuitry, during operation of the circuit block the circuit block presenting a varying load on the output node. Oscillation circuitry is also coupled to the output node to provide an additional load on the output node, and is configured to produce an oscillation signal whose frequency varies as the value of the on-chip voltage supply varies. Control circuitry is configured to be responsive to a trigger condition to adjust the additional load provided on the output node by the oscillation circuitry. This provides a particularly simple and effective mechanism for providing an additional load on the output node which can be altered with the aim of offsetting variation in the load on the output node presented by the circuit block, thus allowing the variation in the voltage output from the on-chip voltage generation circuitry to be controlled.

Integrated circuit and method for controlling load on the output from on-chip voltage generation circuitry

An integrated circuit has a first and second voltage supply rails with first and second voltage levels and a gated voltage supply rail. Each of the circuit elements is connected either between the first and second voltage supply rails or between the gated rail and the second voltage rail. A source circuit structure comprising one or more circuit elements provides an input signal maintained at a static value during a power gated mode of operation. At least one recipient circuit structure requires receipt of the input signal at the static value during the power gated mode of operation. A distribution network comprises a first subset of circuit elements which pull their output to the first voltage level then the input signal has the static value, and a second subset of circuit elements which pull their output to the second voltage level when the input signal has the static value.

Integrated circuit and method for generating a layout of such an integrated circuit

A D-type flip-flop includes tristate inverter circuitry passing a processing signal through to storage circuitryfrom where the processing signal passes via a transmission gate to slave storage circuitry. A transition detector is coupled to the input node of the storage circuitry and serves to generate an error signal if a transition is detected upon that input node during an error detecting period. Other forms of this technique may provide clock gating circuitry.

Signal value storage circuitry with transition detector

An integrated circuit, a method of generating a layout of such an integrated circuit using standard cells, and a standard cell library providing such standard cells, are disclosed. The method of generating the layout comprises forming a plurality of rows, and populating each row with a plurality of standard cells chosen in dependence on the functional components required by the integrated circuit, each standard cell having its abutment area abutting the abutment area of at least one adjacent standard cell in the row. Within each row, each standard cell in that row is arranged to have a voltage connection area that is aligned with a common routing track, but with each standard cell having its voltage connection area configured so as not to extend across the entire width of the standard cell. Within each row, for each standard cell in the row, the voltage connection area of that standard cell is then connected to one of a plurality of voltage supplies having regards to a voltage requirement of the corresponding functional component defined by the standard cell, and independent of the voltage supply to which each adjacent cell in the row is connected. This provides a particularly flexible mechanism for placing standard cells during the layout operation, since standard cells that are required to run off the same voltage supply no longer need to be placed together.

Integrated circuit, method of generating a layout of an integrated circuit using standard cells, and a standard cell library providing such standard cells

A power controlling integrated circuit cell is provided within an integrated circuit power grid to selectively couple an unswitched power supply input to a switched power supply output. The power controlling integrated circuit cell also includes a power control signal input and a power control signal output for supporting the distribution through the integrated circuit of the power control signal. The power controlling integrated circuit cell has a power switching circuit responsive to a power control input signal received at the power control signal input to selectively connect the switched power supply output to the unswitched power supply input, and a power control signal buffer circuit responsive to the switched power supply output to drive a power control output signal from the power control signal output.

Power controlling integrated circuit cell

An integrated circuit is provided with a main supply rail and a virtual supply rail connected by strong and weak header transistors. A power-on controller controls the switching on of the strong transistors after the virtual supply rail voltage has already been driven up to close to its operating level by the weak transistor. The power-on controller comprises a comparator monitoring a single reference voltage level with its output being latched within a latch and used to switch on the strong transistor. The comparator may be programmable to detect multiple different trigger voltage levels by using opposing charging and discharging transistors with one set of these operating in a saturated regime and the other in a regime in which the current therethrough varies in dependence upon the voltage being sensed. These opposing transistors can be used to charge or discharge a node with the state of that node being taken to generate the sensed output.

Integrated circuit power-on control and programmable comparator

Leakage current from a circuit for handling data is reduced using leakage control circuit operable in a leakage reduction mode. The data handling circuit comprises data handling logic operable to receive an input data value and to output and output data value. The data handling circuit also comprises a latch operable to latch the output data value in response to a clock signal having a clock period. Both the leakage control circuitry and the latch are controlled dependent upon the same clock signal and the leakage control circuitry is controlled such that it is in a leakage reduction mode for a time less than the clock period. This approach enables leakage reduction to be provided in circuits which are still operational and is particularly suited to data handling circuits that employ frequency scaling.

Leakage mitigation logic

A latch circuitis described including a function path latch, which may be in the form of a standard flip-flop, together with a data retention latch. The reset signal nreset and the scan enable signal SE are used to control these latches to perform reset, scan, save and restore functions. The save and restore functions serve to save a data value dv from the functional path latchinto the data retention latchand restore this value such that the functional path latch can be powered down without a loss of data.

Latch circuit including a data retention latch

The present invention provides a data processing apparatus comprising a precharged circuit having at least one input line arranged to be precharged to a first logic value during a precharge phase, and a conditional-invert circuit connected to a first at least one input line and arranged to provide a first data value or the inverted first data value on the first input line during an active phase following the precharge phase. The conditional-invert circuit comprises a signal line coupled to the first input line and arranged to be precharged to a predetermined logic value during the precharge phase, a first set of logic gates connected between the signal line and a predetermined voltage, and being arranged upon receipt of a select signal to cause the first data value to be provided on the first input line, and a second set of logic gates connected between the signal line and the predetermined voltage, and being arranged upon receipt of a select signal to cause the inverted first data value to be provided on the first input line. In the active phase, either the first set of logic gates or the second set of logic gates is arranged to receive the select signal. In accordance with the present invention, the speed benefits of using a precharged circuit as opposed to a non-precharged circuit can be realised in circuitry that also requires a conditional-invert function.

Conditional invert functions in precharged circuits

A data memory is described in which data words comprising access control bits and further bits are stored at each memory location 34. When a particular memory location is addressed, then the access control bits stored at that memory location are output to control logic 12, 46 that serves to generate a valid access signal. The valid access signal is fed back to the selected memory location and controls whether the further bits stored at that memory location are output. If access to those further bits is not permitted by the access control bits, then the further bits are not output and power is saved. The control logic is responsive to hardware and software flags in addition to the access control bits. The system is particularly suited for use in conjunction with a cache memory.

Data storage apparatus and method with two stage reading

A memory circuit, in which test data are compared with stored data, comprises a plurality of memory cells each having two complementary data outputs indicative of a respective stored bit of the stored data. The two complementary outputs are selectively interchanged, in response to a respective test bit of the test data. An output signal is then generated (e.g. by a sense amplifier) in response to the relative polarities of the two complementary data outputs. The output signal is indicative of whether the stored bit is equal to the test bit. Where a multi-bit word is stored in a plurality of the memory cells, the output signals generated by a comparison of each stored bit of the multi-bit word and respective bits of the test data are combined by, for example, an AND gate. The output of the AND gate indicates whether the test data matches the stored multi-bit word.

Memory circuit

An output signal driver is described in which a functional block 10, such as a random access memory, provides a data signal to one input of a multiplexer 26 and then via a buffer stage 24 to an output signal line 6. The other input of the multiplexer 26 receives a recirculated value from the output signal line 6. In operation, the buffer stage 24 is enabled as soon as the functional block 10 is enabled. A data valid signal dv indicating when the data signal from the functional block is ready for output is used to switch the multiplexer 26 from selecting the recirculated value to selecting the new data signal value. The output signal on the output signal line 6 is made to always have a defined state derived from the existing output signal level or, when it becomes available, the new data signal. Power wastage through the driving of spurious signals on the output signal line 6 is thus avoided.

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Cambridge, United Kingdom

David William Howard