Massachusetts Institute of Technology

David Whelihan

Daniil M Utin

Roger I Khazan

Joshua Kramer

Mankuan Michael Vai

Paul S Keltcher

Scott M Sawyer

Jeffrey J Hughes

A circuit for secure operation includes a plurality of mutually exclusive circuit zones including a first circuit zone having a first level of security and a second circuit zone having a second level of security less than the first level of security and one or more gate circuits each providing limited transfer of data between the circuit zones, the gate circuits providing all data connectivity between the first circuit zone and the second circuit zone and statically configured to prevent unmodified transfer of data from the first circuit zone to the second circuit zone.

Data security using inter-zone gate circuits

A method for processing addressable encrypted data representing addressable cleartext data uses an integrated circuit including a processor circuit. The method includes processing the addressable cleartext data in the processor circuit without storing said cleartext data outside the processor circuit.

Secure execution of encrypted software in an integrated circuit

A method for operating a secure device having a plurality of mutually exclusive circuit zones, including a first circuit zone having a first level of security and a second circuit zone having a second level of security less than the first level of security, the method including unpacking a key exchange package including receiving a key exchange package in the second circuit zone, the key exchange package including encrypted key data and processing the encrypted key data using a content key in the first circuit zone to generate decrypted key data and storing the decrypted key data in the first circuit zone without disclosing the decrypted key data into the second circuit zone.

Cryptography and key management device verification

Global synchrony changes the way computers can be programmed. A new class of ISA level instructions (the globally-synchronous load-store) of the present invention is presented. In the context of multiple load-store machines, the globally synchronous load-store architecture allows the programmer to think about a collection of independent load-store machines as a single load-store machine. These ISA instructions may be applied to a distributed matrix transpose or other data that exhibit a high degree of data non-locality and difficulty in efficiently parallelizing on modern computer system architectures. Included in the new ISA instructions are a setup instruction and a synchronous coalescing access instruction ('sca'). The setup instruction configures a head processor to set up a global map that corresponds processor data contiguously to the memory. The 'sca' instruction configures processors to block processor threads until respective times on a global clock, derived from the global map, to access the memory.

ISA extensions for synchronous coalesced accesses

A method for limiting execution of an encrypted computer program on a secure processor includes executing a first set of instructions encoding a test for determining whether a value of a register of the secure processor belongs to a set of valid register values encoded in the encrypted computer program. Execution of the first set of instructions causes the secure processor to read a first register value from the register of the secure processor, the register of the secure processor preventing repeated reads of a same value of the register, and determine whether the first register value belongs to the set of valid register values encoded in the encrypted computer program. Execution of further instructions of the encrypted computer program is prevented if the first register value does not belong to the set of valid register values encoded in the encrypted computer program.

Limted execution of software on a processor

Cryptography and key management device and architecture

Data locality constraints are alleviated by a data processing system and method of reorganizing data. Multiple electronic components are configured to modulate a light beam on a shared photonic interconnect and to detect the data according to a global schedule to reorganize data across the multiple electronic components. By constructing data transfer patterns in a shared photonic interconnect, rather than in dedicated reorganization hardware, data is reorganized while in transit, greatly accelerating the reorganization of data, and reducing the amount of power-consuming hardware necessary to achieve the task.

Growing community of inventors

Framingham, MA, United States of America

David Whelihan