International Business Machines Corporation

David Wells Winston

Tong Li

Richard Daniel Kimmel

Pravin Kamdar

David James Hathaway

Vasant B Rao

Jeffrey Paul Soreff

Ali Sadigh

Dureseti Chidambarrao

Richard Quimby Williams

James Douglas Warnock

Ronald Dennis Rose

Peter Feldmann

Bhavna Agrawal

Calvin John Bittner

Sang Y Lee

Karl K Moody, Iii

Peng Peng

System analysis by receiving a model of a complex system design. The model includes at least one layer. The analysis includes performing a plurality of simulations of the performance of the layer. The number of simulations is determined according to a number of system components associated with the layer. The analysis further includes determining a worst-case result for a set of simulations from the plurality of simulations and assigning the worst-case result to an overall system simulation.

Multi-rate sampling for hierarchical system analysis

Methods, systems, and computer program products for machine learning model decision boundary enhancement are provided. Aspects include determining a decision boundary associated with a first machine learning model, wherein the first machine learning model is trained with an initial training set of features and associated classifications from a verification model, obtaining a plurality of new feature sets, analyzing, by the first machine learning model, the plurality of new feature sets to determine that a subset of feature sets have classification predictions within a threshold range of the decision boundary associated with the first machine learning model, inputting the subset of feature sets into the verification model to determine enhanced training data based on outputs of the verification model, and creating an enhanced machine learning model by further training the first machine learning model with the initial training data and the enhanced training data.

Decision boundary enhancement for learning models

Systems and methods of developing an integrated circuit implement selecting a desired yield for a circuit used in the integrated circuit. The desired yield corresponds to a desired failure probability of the circuit. The method includes determining a parameter threshold value that corresponds with the desired yield. The circuit passes if a parameter associated with the circuit is below the parameter threshold value and the desired yield indicates a percentage of instances of the circuit that pass according to the parameter threshold value. The method also includes using the parameter threshold value that corresponds with the desired yield during testing and improvement of a design of the integrated circuit, and providing the design of the integrated circuit for fabrication.

Iterative approach to determine failure threshold associated with desired circuit yield in integrated circuits

Methods, systems, can computer program products for optimizing statistical method of computing output yields are provided. Aspects include determining a target criteria of a system for statistical analysis, based on the target criteria, determining a statistical analysis algorithm for the simulation, determining a block size for a plurality of statistical samples of the system for a parallelization of the statistical analysis algorithm, generating the plurality of statistical samples of the system, simulating the plurality of statistical samples of the system to determine one or more output yields, calculating a confidence interval for each of the one or more output yields, wherein the confidence interval comprises a lower bound, comparing the lower bound to a threshold standard deviation of a probability density function, and adjusting the block size for the plurality of statistical samples based on determining that the lower bound is less than the threshold standard deviation.

Adaptive accelerated yield analysis

An on-demand table model for semiconductor device evaluation is provided. A method of providing on-demand table models for semiconductor device evaluation, includes measuring one or more measurement values of an instance of a semiconductor device. The method further includes providing, by a processor, a table model of the instance for the semiconductor device evaluation upon receiving a request for the semiconductor device evaluation. The method further includes generating a table entry in the table model for the one or more measurement values, the table entry including one or more evaluation values of an evaluation function for the instance.

On-demand table model for semiconductor device evaluation

A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load CCC for a transition or state of a driving CCC for which a load condition is being determined; a trace system that traverses paths in the load CCC from a set of input terminals; and an element replacement system that replaces circuit elements in the load CCC to create a modeled CCC, wherein a circuit element replacement is based on a type of circuit element encountered along a trace, and state and transition functions of nets connected to an encountered circuit element.

Modeling loading effects of a transistor network

Disclosed are embodiments of a system and of an associated method for estimating the leakage current of an electronic circuit. The embodiments analyze a layout of an electronic circuit in order to identify all driven and non-driven nets within the electronic circuit, to identify all of the driven net-bounded partitions within the electronic circuit (based on the driven and non-driven nets), and to identify, for each driven net-bounded partition, all possible states of the electronic circuit that can leak. Then, using this information, the embodiments estimate the leakage current of the electronic circuit. This is accomplished by first determining, for each state of each driven net-bounded partition, a leakage current of the driven net-bounded partition and a probability that the state will occur in the driven net-bounded partition during operation of the electronic circuit. Then, for each state of each driven net-bounded partition, the leakage current of the driven net-bounded partition and the state probability are multiplied together. The results are then aggregated.

System and method for estimating leakage current of an electronic circuit

A layout of a semiconductor circuit is analyzed to calculate layout-dependant parameters that can include a mobility shift and a threshold voltage shift. Layout-dependant effects that affect the layout dependant parameters may include stress effects, rapid thermal anneal (RTA) effects, and lithographic effects. Intrinsic functions that do not reflect the layout-dependant effects are calculated, followed by calculation of scaling modifiers based on the layout-dependant parameters. A model output function that reflects the layout-dependant effects is obtained by multiplication of each of the intrinsic functions with a corresponding scaling parameter.

System and methodology for determining layout-dependent effects in ULSI simulation

The present invention provides for simulating signal transitions. Circuit characteristics are generated. Circuit characteristics are loaded into memory. Circuit behaviour is simulated. A non-leading edge circuit transition is captured. This occurs in software.

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Asheville, NC, United States of America

David Wells Winston