Lam Research Corporation

Vbridge Microsystem, Inc.

David Wei

Yehiel Gotkis

John Boyd

Sean S Kang

Rodney C Kistler

Xuyen Pham

Tony Luong

Aleksander Owczarz

Anthony De La Llera

Cangshan Xu

Vinay Pohray

Bi Ming Yen

Binet A Worsham

Aleksander Owzarz

Tuan Anh Nguyen

Eric A Hudson

Kenji Takeshita

Miguel Angel Saldana

Stephen M Sirard

Damon Vincent Williams

Rod Kistler

Ren Zhou

Sridharan Srivatsan

Katgenhalli Y Ramanujam

Linda Jiang

Howard Dang

Joseph P Simon

Mayumi Block

Masahiro Watanabe

Anjun Jerry Jin

A method of dechucking a wafer, with a low-k dielectric layer, held onto an electrostatic chuck by an electrostatic charge in a plasma chamber is provided. The electrostatic clamping voltage is removed. An essentially argon free dechucking gas is provided into the plasma chamber. A dechucking plasma is formed from the dechucking gas in the plasma chamber. The dechucking plasma is stopped.

Wafer electrical discharge control using argon free dechucking gas

Methods of fabricating semiconductor structures on a substrate, where the substrate has transistors formed thereon, are provided. One method includes forming interconnect metallization structures in a plurality of levels. The forming of the interconnect metallization structures includes depositing a sacrificial layer and performing a process to etch trenches, vias, and stubs into the sacrificial layer. The method further includes filling and planarizing the trenches, vias, and stubs that were etched and then etching away the sacrificial layer throughout the plurality of levels of the interconnect metallization structures. The etching leaving a voided interconnect metallization structure that is structurally supported by stubs that are non-electrically functional.

Method for making semiconductor structures implementing sacrificial material

A method for etching features in a silicon oxide based dielectric layer over a substrate, comprising performing an etch cycle. A lag etch partially etching features in the silicon oxide based dielectric layer is performed, comprising providing a lag etchant gas, forming a plasma from the lag etchant gas, and etching the etch layer with the lag etchant gas, so that smaller features are etched slower than wider features. A reverse lag etch further etching the features in the silicon oxide based dielectric layer is performed comprising providing a reverse lag etchant gas, which is different from the lag etchant gas and is more polymerizing than the lag etchant gas, forming a plasma from the reverse lag etchant gas, and etching the silicon oxide based dielectric layer with the plasma formed from the reverse lag etchant gas, so that smaller features are etched faster than wider features.

Lag control

A method for making a semiconductor device is provided. The method includes forming transistor structures on a substrate and forming interconnect metallization structures in a plurality of levels through depositing a sacrificial layer. A dual damascene process is performed to etch trenches and vias, and filling and planarizing the trenches and vias. The sacrificial layer is etched throughout the plurality of levels of the interconnect metallization structures, thus leaving a voided interconnect metallization structure. The voided interconnect metallization structure is filled with low K dielectric material, thus defining a low K dielectric interconnect metallization structure.

Semiconductor structure implementing sacrificial material and methods for making and implementing the same

A system-on-chip (SoC) for voice and video over data network applications includes a first and a second general purpose processors and a plurality of coprocessors. The coprocessors include: a VCODEC engine for video compression/decompression, a security engine for data encryption/decryption, a network processor for processing data packets, a video scaling controller for scaling up/down video frames, and digital signal coprocessors for signal processing and audio codec. An on-chip shared memory (e.g., SRAM) is coupled to the processors and some of the coprocessors. The SoC also includes: i) a stream controller for controlling various properties of a stream buffer in the shared memory according to a user defined context; ii) a transaction management engine for managing data especially stream transactions in accordance with one or more task queues created by the processors; and iii) a bi-directional stream bus coupled to the shared memory and a plurality of peripheral controllers.

SoC architecture for voice and video over data network applications

An air platen assembly is described and includes a platen that has a plurality of concentric rings. Each of the rings has a plurality of openings in order to provide a cushion of air to a CMP belt. At least one of the rings extends beyond an outer edge of a wafer to be planarized by the CMP belt. A support is attached with the platen and has a plurality of air ports for pressurized air to pass to the rings of the platen. A gasket is positioned between the support and the platen and has a plurality of cutouts that align with the openings and the air ports. A base is also included and supports the support.

Air platen for leading edge and trailing edge control

A semiconductor device is provided. The semiconductor device includes a substrate having transistor devices and a plurality of copper interconnect metallization lines and conductive vias. The plurality of copper interconnect metallization lines and conductive vias are defined in each of a plurality of interconnect levels of the semiconductor device such that the plurality of copper interconnect metallization lines and conductive vias are isolated from each other by an air dielectric. The semiconductor device further includes a plurality of supporting stubs each of which is configured to form a supporting column that extends through the plurality of interconnect levels of the semiconductor device.

Semiconductor structure implementing low-K dielectric materials and supporting stubs

A chemical mechanical planarization (CMP) system is provided. The system includes a polishing surface and a platen disposed along an underside of the polishing surface. A retaining ring surrounds the platen. The retaining ring includes a lower annular sleeve and an upper annular sleeve moveably disposed over the lower annular sleeve. A method for reducing a consumption of compressed dry air (CDA) during a chemical mechanical planarization (CMP) operation is also described.

Apparatus for reducing compressed dry air usage during chemical mechanical planarization

A temperature controlling system for use in a chemical mechanical planarization (CMP) system having a linear polishing belt, a carrier capable of applying a substrate over a preparation location over the linear polishing belt is provided. The temperature controlling system includes a platen having a plurality of zones. The temperature controlling system further includes a temperature sensor configured determine a temperature of the linear polishing belt at a location that is after the preparation location. The system also includes a controller for adjusting a flow of temperature conditioned fluid to selected zones of the plurality of zones of the platen in response to output received from the temperature sensor.

Method and apparatus for heating polishing pad

An apparatus for reducing non-uniform stretch of a belt used in the CMP system is disclosed. The belt that may be used with the apparatus extends between a first roller and a second roller to define a belt loop with an inner surface and an outer surface to be used for CMP. The apparatus includes a compensating roller that has a first end and a second end where the first end and second end extends a width of the belt. The first end and the second end have a first diameter. The center of the roller has a second diameter that is less than the first diameter. The compensating roller has a symmetrically tapered shape that extends between each of the first end and second end to the center. The compensating roller is positioned inside of the belt loop, and is applied to the inner surface of the belt loop to reduce non-uniform stretch of the belt.

CMP belt stretch compensation apparatus and methods for using the same

An invention is provided for removal rate profile manipulation during a CMP process. An apparatus of the embodiments of the present invention includes an actuator capable of vertical movement perpendicular to a polishing surface of a polishing pad. The actuator is further capable of flexing the polishing pad independently of a pad support device. Also included in the apparatus is an actuator control mechanism that is in communication with the actuator. The actuator control mechanism is capable of controlling an amount of vertical movement of the actuator, allowing the actuator to provide local flexing of the polishing pad to achieve a particular removal rate profile. The actuator can also be capable of horizontal movement parallel to the polishing surface of the polishing pad.

Apparatus for removal/remaining thickness profile manipulation

A chemical mechanical planarization (CMP) system having a polishing pad, a carrier body for holding a wafer, a retaining ring, and an active retaining ring support is provided. The active retaining ring is defined by a circular ring having a thickness and a width. The circular ring is defined by an elastomeric material. The circular ring is configured to be placed between the retaining ring and the carrier body. The circular ring has a plurality of voids therein, and the plurality of voids are defined in locations around the circular ring. The circular ring has a compressibility level that is set by the elastomeric material and the plurality of voids.

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Fremont, CA, United States of America

David Wei