Agere Systems Inc.

David Wayne Potter

Hyun K Lee

Michael James Hunter

Lai Q Pham

A bidirectional bus repeater is disclosed that connects individual segments of a bidirectional bus. The exemplary bidirectional bus repeater consists of a direction control block and a buffer block. The buffer block contains one pair of buffers for each bus bit and an extra pair associated with the indicator lines. Indicator lines are used by the direction control block based on activity on the bus to generate control signals (control-A and control-B) that control the state of the tri-state buffers. In an exemplary embodiment, each node must toggle the indicator line whenever the node drives the bus. When the bus is inactive, the control-A and control-B signals generated by the direction control block are both inactive because the voltages on both sides of the bidirectional bus repeater are the same. When the direction control block detects a change of voltage on the indicator line associated with one side of the bus (e.g., indicator-A associated with bus-A), the corresponding tri-state buffers are enabled. Thereafter, the opposite bus segment (bus-B) is driven by the repeater buffers, until the bus segment bus-B reaches the same logic level as the bus segment bus-A. The logic level on indicator-B also changes to the same logic level as indicator-A. Eventually, both segments of the bus wire and the indicator wires connected to the bidirectional bus repeater circuit are equal and the DC turns off the a control signal A (cntl-A).

Bidirectional bus repeater for communications on a chip

The present invention is a method and apparatus for dynamically holding valid data logic levels on a bus by taking advantage of the inherent storage capacity of the bus. The bus speed is increased by eliminating the use of active bus keepers and null cycles. Instead, a two phase clock is used, the bus drivers drive data onto the bus during the first phase of the clock and are turned off at the beginning of the second phase of the bus clock. The receiving device latches the data during the second phase of the bus clock. Accordingly, there is no need for a null cycle or a bus keeper circuit, yet there is no bus contention between consecutive drivers nor is there a floating node condition.

Method and apparatus for using a bus as a data storage node

A method and apparatus for arbitrating access to a bus such that the bus can operate at a variable data rate, that rate being the rate of the slower of the two devices communicating over the bus. The smart arbiter in accordance with the invention has knowledge of the speed of the devices that use the bus and grants access in an order and at a rate based on that information. The smart arbiter can intersperse grants such that data transfers between multiple pairs of transmitting and receiving devices that are not independently utilizing the maximum bandwidth capabilities of the bus can overlap. Thus, if one pair of devices are exchanging multiple consecutive words (or other units of data) at a rate slower than the maximum rate of the bus, another pair of devices can use some of the bus clock cycles between the transfer of words of the first device pair, for transfers of words between the second device pair.

Data bus method and apparatus providing variable data rates using a smart bus arbiter

The present invention comprises a clocked bus keeper circuit that does not drive the bus during the first half of a clock cycle and then holds the value driven onto the bus during the first half of the clock cycle for the second half of the clock cycle. Accordingly, true data drivers on the bus drive the bus during the first half of the clock cycle without the need to overcome the value driven by the bus keeper, but during the second half of the clock cycle, the bus keeper holds the data driven during the first half of the clock cycle. In this manner, there is no bus contention between the true bus data drivers and the bus keeper.

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Allentown, PA, United States of America

David Wayne Potter