Taiwan Advanced Sensors Corporation

David Wayne

Sywe N Lee

A structure of an image sensor for sensing the light of an image impinging thereupon and for translating the image into a standard television format is disclosed. The structure comprises a plurality of first and second light detecting elements () arranged in rows and columns and half as many rows and columns as scan lines of a television format for generating respective analog signals in proportion to the intensity of the light impinging respectively on each of the first and second light detecting elements (), wherein the first and second light detecting elements in each row are alternately disposed and activated by first read lines RDOn (n=1 . . . 256) to generate odd field signals, and wherein the first and second light detecting elements () of two adjacent rows disposed in a zigzag or serrated manner are activated by second read lines RDEn (n=1 . . . 256) to generate even field signals.

Interlaced alternating pixel design for high sensitivity CMOS Image sensors

In a CMOS-type image sensor, a plurality of pairs of light-detecting elements (LDEs) are arranged in rows and columns to generate analog signals proportional to the intensity of light impinging on respective one of the LDEs. First and second photo sensing means in each pair of LDEs are coupled in parallel, in the column direction, at a floating sensing point through first turn-on means. The first and second photo sensing means in adjacent pairs of LDEs are coupled in parallel in the column direction through second turn-on means. The first turn-on means are enabled by first control lines and the second turn-on means are enabled by second control lines coupled thereto, respectively. Analog signals acquired in the first and second photo sensing means of one pair or of adjacent pairs are present at the floating sensing point in response to the enabling of the first or second control lines, respectively.

Interlace overlap pixel design for high sensitivity CMOS image sensors

A self-compensating correlated double sampling circuit for a pixel image signal and a method to process the same. In the circuit, the analog signal generated by the photosensor of the pixel array accessed by a row selection transistor is buffered through a source follower amplifier and coupled to a column in the array. The analog signal from the selected column line is fed through a CDS circuit which is then input to the sample and hold circuit of the ADC. The main purpose of the CDS circuit is to reduce the noise and non-uniformity caused by the non ideal effects associated with the signal path from the photosensor through the CDS circuit. This is accomplished by sampling the signal and a reference level and then performing the subtraction on the two samples and the ADC ramp through the same signal path.

Growing community of inventors

Scottsdale, AZ, United States of America

David Wayne