International Business Machines Corporation

Cadence Design Systems, Inc.

David Warren Pruden

William Eric Hall

Brian Andrew Schuelke

Dennis Martin Rickert

Brian P Deskin

Paul Chang

A method and apparatus for implementing integrated circuit security features are provided to selectively disable testability features on an integrated circuit chip. A test disable logic circuit receives a test enable signal and responsive to the test enable signal set for a test mode, establishes a test mode and disables ASIC signals. Responsive to the test enable signal not being set, the ASIC signals are enabled for a functional mode and the testability features on the integrated circuit chip are disabled. When the functional mode is enabled, the test disable logic circuit prevents the test mode from being established while the integrated circuit chip is powered up.

Implementing logic security feature for disabling integrated circuit test ports ability to scanout data

A method and eFuse circuit for implementing enhanced security features using eFuses, such as disabling selected predefined test, debug, and mission security functions used in application-specific integrated circuits (ASICs), and a design structure on which the subject circuit resides are provided. The eFuse circuit includes a plurality of eFuses, a sense amplifier coupled to the plurality of eFuses, and a plurality of sense output latches coupled to the sense amplifier. The plurality of sense output latches is arranged to have a bias to power up to a known value. Control logic coupled to the plurality of sense output latches provides at least one predefined control signal responsive to the known value of the plurality of sense output latches, which enables a selected predefined security function. The plurality of eFuses is sensed and the ASIC is configured to a predefined state responsive to an applied POR/Sense control signal.

Implementing enhanced security features in an ASIC using eFuses

A method is defined which reduces the number of applied test patterns while maintaining identical fault coverage for a given set of weighted random patterns. Reduction is accomplished by simulating the weight sets in reverse order against a full (untested) fault list but allowing fault mark-off for initially effective patterns only (patterns which detected faults). This results in some patterns which initially detected only a few faults (due to their exposure to a small untested fault list) to detect a greater number of faults (due to their exposure to a full fault list), while other patterns which were initially effective become ineffective (detected no faults). Since the same faults are still detected there is no loss of coverage. Only those patterns which remain effective after exercising the reverse simulation are ultimately applied on the tester.

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Endwell, NY, United States of America

David Warren Pruden