Intel Corporation

David Walter Young

Thomas Dory

Michael N Derr

Leigh E Wojewoda

HengGee Lee

Embodiments of a cryptograph processing device and method for adapting to shared-cache attacks are generally described herein. Other embodiments may be described and claimed. In some embodiments, the cryptographic processing device comprises first and second processing units, and a cache that is shared by the first and second processing units. The first processing unit may monitor a number of cache misses that occur during the performance of a first cryptographic process and may switch to performing a second cryptographic process after the number of cache misses exceeds a threshold.

Cryptographic processing device and method for adapting to shared-cache attacks

Embodiments of the invention are generally directed to a methods, apparatuses, and systems for quiescing a processor bus agent. In one embodiment, a processor initiates the establishment of a protected domain for a computing system. A processor bus agent coupled with the processor is quiesed to reduce the potential for interference with the establishment of the protected domain. Other embodiments are described and claimed.

Quiescing a manageability engine

Embodiments of system and method for adapting to attacks of cryptographic processes on multiprocessor systems with shared cache are generally described herein. Other embodiments may be described and claimed.

System and methods for adapting to attacks on cryptographic processes on multiprocessor systems with shared cache

An apparatus, comprising: a substrate having a surface; a die attached to the substrate surface; an underfill material positioned between the substrate surface and the die; and one or more barriers on the substrate surface adjoining the die, wherein the barriers controls flow of the underfill material.

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Portland, OR, United States of America

David Walter Young