Netlogic Microsystems, Inc

Altera Corporation

Alcatel Canada Inc.

Integrated Device Technology, Inc.

Alcatel-lucent Canada Inc.

Other

Newbridge Networks Corporation

Silicon Access Networks, Inc.

David Walter Carr

Paul Nadj

Edward D Funnekotter

Gary Michael Depelteau

Jason T Sterne

Robert G James

Denny L S Lee

Sandra Stark

Subramani Kengeri

Denny L Lee

Jaya Prakash Samala

Joey M W Chow

Tingjun Wen

Tadeusz Kwasniewski

Joey M Chow

A method for high-speed scheduling and arbitration of events for computing and networking is disclosed. The method includes the software and hardware implementation of a unique data structure, known as a pile, for scheduling and arbitration of events. According to the method, events are stored in loosely sorted order in piles, with the next event to be processed residing in the root node of the pile. The pipelining of the insertion and removal of events from the piles allows for simultaneous event removal and next event calculation. The method's inherent parallelisms thus allow for the automatic rescheduling of removed events for re-execution at a future time, also known as event swapping. The method executes in O() time.

System and method for scheduling and arbitrating events in computing and networking

A pipelined search engine supports a tree of search keys therein that utilizes span prefix masks to assist in longest prefix match (LPM) detection when the tree is searched. Each of a plurality of the span prefix masks encodes a prefix length of a search key to which the span prefix mask is associated and a value of another search key in the tree that is a prefix match to the search key to which the span prefix mask is associated.

Integrated search engine devices that support LPM search operations using span prefix masks that encode key prefix length

An integrated search engine device evaluates span prefix masks for keys residing at leaf parent levels of a search tree to identify a longest prefix match to an applied search key. This longest prefix match resides at a leaf node of the search tree that is outside a search path of the search tree for the applied search key. The search engine device is also configured to read a bitmap associated with the leaf node to identify a pointer to associated data for the longest prefix match. The pointer has a value that is based on a position of a set bit within the bitmap that corresponds to a set bit within the span prefix mask that signifies the longest prefix match.

Integrated search engine devices that utilize SPM-linked bit maps to reduce handle memory duplication and methods of operating same

A method for high-speed scheduling and arbitration of events for computing and networking is disclosed. The method includes the software and hardware implementation of a unique data structure, known as a pile, for scheduling and arbitration of events. According to the method, events are stored in loosely sorted order in piles, with the next event to be processed residing in the root node of the pile. The pipelining of the insertion and removal of events from the piles allows for simultaneous event removal and next event calculation. The method's inherent parallelisms thus allow for the automatic rescheduling of removed events for re-execution at a future time, also known as event swapping. The method executes in O(1) time.

Methods of operating a search engine device include repeatedly reading next keys (and associated handles) from a database within the search engine device in order to identify and transfer some or possibly all of the contents of the database to another device (e.g., command host) requesting the database contents. An operation to read a next key includes: (i) searching a pipelined database within the search engine device with a first key to identify at least one key therein that is greater than the first key and then (ii) executing a next key fetch operation in the pipelined database to identify the next key from the at least one key. The next key and a handle associated with the next key are then retrieved from the search engine device (e.g., transferred to a command host).

Integrated search engine devices that support database key dumping and methods of operating same

A system that includes a host and a peripheral device. The host transmits a packet that includes a command and a flow control field. The peripheral device receives the packet and has the ability to execute the command, wherein the peripheral device can determine whether the command can be processed in a timely manner, and can update the packet's flow control field with flow control data based on the determination. The host receives the updated packet and has the ability to adjust the flow control of subsequent packets to the peripheral device based on the flow control data in the updated packet.

Method of handling flow control in daisy-chain protocols

An integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a first n-bit operand (e.g., A[n&#x2212;1, . . . , 0]) and a second n-bit operand (e.g., B[n&#x2212;1, . . . , 0]). The comparator cell determines the non-strict inequality by computing a control output signal C(or its complement), where: 'n' is a positive integer greater than one and Cis a control input signal that specifies an interpretation to be given to the control output signal C.

Packet processors having comparators therein that determine non-strict inequalities between applied operands

A search engine device that supports a Patricia trie arrangement of search keys includes an array of comparator cells that supports parallel decoding of the Patricia trie. This array of comparator cells processes a plurality of distinguishing bit identifiers for nodes in the Patricia trie in parallel with a corresponding plurality of bits of an applied search key during a search operation. In response to this processing, the array generates a match signal that identifies a location of a matching search key candidate within the Patricia trie.

Search engine devices that support high speed parallel decoding of digital search tries

A method for improving the speed and efficiency of transmitting data between two components in which the transmitted data is sent, at least partly, through a serial bus is shown. According to the method, the fields in the data frames being transmitted between the components are of a fixed length regardless of the amount of data that the receiving device can receive at one time. The data bits of the fixed-length frame correspond to the signals accepted as input by the receiving component.

Method for deterministic timed transfer of data with memory using a serial interface

A search engine device includes a hierarchical memory that is configured to store a b-tree of search prefixes and span prefix masks (SPMs). These SPMs are evaluated during each search operation to identify search prefixes that match an applied search key yet reside at nodes of the b-tree that are not traversed during the search operation. The search engine device also includes handle memory. This handle memory is configured to support a respective handle memory block for each search prefix within each of a plurality of nodes of the b-tree that reside at a leaf parent level within the b-tree. Each of these handle memory blocks may have sufficient capacity to support one result handle per bit within a span prefix mask associated with a corresponding search prefix. In other cases, each of these handle memory blocks may have sufficient capacity to support only M+1 handles, where M is a positive integer corresponding to a quantity of search prefixes supported by each of a plurality of leaf nodes within the b-tree.

Integrated search engine devices that utilize hierarchical memories containing b-trees and span prefix masks to support longest prefix match search operations

An integrated circuit memory system includes a write-back buffer and a control circuit that support read-write-modify (RWM) operations within a high capacity memory device. A RWM operation may include reading from the integrated circuit memory device and the write-back buffer to identify whether the memory device or the write-back buffer has the data requested by a read instruction issued to the memory system. The data read from the write-back buffer is then written into the memory device and a modified version of the requested data is written to the write-back buffer in anticipation of subsequent transfer to the memory device.

Integrated circuit memory systems having write-back buffers therein that support read-write-modify (RWM) operations within high capacity memory devices

A search engine includes a pipelined arrangement of a plurality of search and tree maintenance sub-engines therein, which are configured to support the performance of search operations on exclusively valid multi-way trees of search prefixes concurrently with the performance of update operations on the multi-way trees as they are being searched.

Integrated search engine devices having pipelined search and tree maintenance sub-engines therein that maintain search coherence during multi-cycle update operations

An improved data structure is provided by modifying a public-domain data structure known as a 'heap'. When these improvements are applied, the resultant data structure is known as a 'pile.' This invention further describes a pipelined hardware implementation of a pile. Piles offer many advantages over heaps: they allow for fast, pipelined hardware implementations with increased throughput, making piles practical for a wide variety of new applications; they remove the requirement to track and update the last position in the heap; they reduce the number of memory reads accesses required during a delete operation; they require only ordinary, inexpensive RAM for storage in a fast, pipelined implementation; and they allow a random mixture of back-to-back insert, remove, and swap operations to be performed without stalling the pipeline.

Data structure and method for pipeline heap-sorting

A pipelined search engine device, such as a longest prefix match (LPM) search engine device, includes a hierarchical memory and a pipelined tree maintenance engine therein. The hierarchical memory is configured to store a b-tree of search prefixes (and possibly span prefix masks) at multiple levels therein. The pipelined tree maintenance engine, which is embedded within the search engine device, includes a plurality of node maintenance sub-engines that are distributed with the multiple levels of the hierarchical memory. The search engine device may also include pipeline control and search logic that is distributed with the multiple levels of the hierarchical memory.

Integrated search engine devices having pipelined search and tree maintenance sub-engines therein that support variable tree height

A pipelined search engine device, such as a longest prefix match (LPM) search engine device, includes a hierarchical memory and a pipelined tree maintenance engine therein. The hierarchical memory is configured to store a b&#x2212;tree of search prefixes (and possibly span prefix masks) at multiple levels therein. The pipelined tree maintenance engine, which is embedded within the search engine device, includes a plurality of node maintenance sub-engines that are distributed with the multiple levels of the hierarchical memory. The search engine device may also include pipeline control and search logic that is distributed with the multiple levels of the hierarchical memory.

Growing community of inventors

Nepean, Canada

David Walter Carr