Infineon Technologies Ag

Other

David Wallis

Axel Brintzinger

Octavio Trovarelli

Manfred Schneegans

Michael Roesner

Barbara Vasquez

Sylvia Baumann Winter

Stefan Ruckmich

Ingo Uhlendorf

Wolfgang Leiberg

Fritz Uhlendorf, Legal Representative

The invention relates to a method for producing a rewiring printed circuit board with a substrate wafer having passage connections between a first and a second surface. One embodiment of the method comprises applying and patterning masking layers on the first and the second surfaces, thereby uncovering a first contact location on the first surface and a second contact location on the second surface; applying a protective layer to the second surface in order to protect the corresponding masking layer and the second contact location during subsequent method steps; applying a first conductor structure to the first surface, the first conductor structure on the first surface covering the first contact location; removing the protective layer on the second surface; and applying a second conductor structure to the second surface, the second conductor structure on the second surface covering the second contact location.

Method for producing a rewiring printed circuit board

An arrangement for protecting fuses/anti-fuses on chips which serve to activate redundant circuits or chip functions includes a passivation layer (e.g., hard passivation) arranged on a fully processed chip with the exception of metal contacts of a metallization level and the fuses. The chip is provided with a redistribution layer that is electrically contact-connected to the metallization level, and to a process for protecting such fuses/anti-fuses. The invention is now based on the object of ensuring sufficient protection of fuses/anti-fuses on integrated circuits. This is achieved by virtue of the fact that a dielectric (), which covers at least the region of the fuses/anti-fuses () and to which the redistribution layer () comprising the combination of materials Cu/Ni/Au is applied, is arranged on the passivation layer ().

Arrangement and process for protecting fuses/anti-fuses

A conductive connection is made between a semiconductor chip and an external conductor structure. An elevation element is applied on the surface of the semiconductor chip and a soldering island is arranged on the elevation element. An interconnect is produced below the soldering island as far as a bonding island or an I/O pad. Increased reliability of conductive connections of the bonding island or the I/O pad to an external conductive structure can be achieved by preventing the flowing-away of the solder and the oxidation or corrosion of the conductive layer.

Connection between a semiconductor chip and an external conductor structure and method for producing it

An apparatus ( ) for wafer grinding includes sensors ( ) and a spectral analyzer to perform a spectral analysis of light received by the sensors ( ) during grinding of a semiconductor wafer ( ). Based on the spectral analysis, the grinding process is stopped or the force applied to the semiconductor wafer is modified. This in situ monitoring decreases breakage and overheating of the semiconductor wafer ( ).

Apparatus for and method of wafer grinding

The present invention provides a new backside treatment of the wafer. Trenches are cut into the top surface of the wafer by sawing or etching, and after grinding the wafer from the bottom side, a protective material is applied as a surface layer to the bottom surface while filling the trenches with this material. The material is hardened in order to accomplish the sawing process. In another embodiment of the present method, a double foil layer is applied to the rear side of the wafer including a mounting tape and a protective layer facing the wafer rear side.

Method of applying a bottom surface protective coating to a wafer, and wafer dicing method

A machining apparatus ( ) comprises a material removing tool ( ) movably mounted for removing material from a workpiece ( ); means for illuminating ( ) a sample area upon a tool surface ( ) with excitation radiation; means for receiving ( ) sample light emitted from the sample area; a spectral analyzer ( ) for performing a spectral analysis of the sample light received; and means for determining ( ) the condition of the tool at the sample area from the spectral analysis of the sample light. The wear of the tool ( ) is determined as such a condition. Operation parameters of the machining apparatus ( ) are adjusted according to the determined wear. An example application is a wafer dicing tool.

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Dresden, Germany

David Wallis