University of Dayton

United States of America as Represented by the Secretary of the Air Force

David Walker

Frank Scarpino

Eric Balster

Thaddeus Marrara

Mike Flaherty

Benjamin Fortener

David Lucking

David Mundy

Ken Simone

William Turri

Nick Vicen

Marc Hoffman

DeJuan Daniels

The present invention generally relates to pulse capture electronics (PCE) of an imaging system that provides the ability to interface with, control, and test Read-Out Integrated Circuits (ROIC), and communicate the image data to a computing device for rendering and/or computational processing. The RIS-DC includes a single board signal processing architecture that is combined with a processor board to enable various operational requirements and varying ROICs to be configured to produce an operational imaging system.

Read-out integrated circuit (ROIC) interface system for digitization and control (RIS-DC)

A system for processing an image includes a an image data input port, a compressed image data output port or a compressed image data storage node, a non-transitory memory component storing a set of executable instructions, and a scalable tile processing device. The executable instructions cause the system to receive image data, partition the image data into tiles, transmit a tile to the scalable tile processing device, receive an encoded bit stream corresponding to the transmitted tile from the tile processing device, and output compressed image data including the encoded bit stream. The scalable tile processing device receives the tile including tile image data, wavelet transforms, quantizes, segments, and encodes the tile image data to generate a plurality of encoded code blocks, and transmits an encoded bit stream including the plurality of encoded code blocks to the system.

Image processing systems employing image compression

A system for processing an image includes a non-transitory memory component storing a set of executable instructions, and a scalable tile processing device. The executable instructions cause the system to receive image data, partition the image data into tiles, transmit a tile to the scalable tile processing device, receive an encoded bit stream corresponding to the transmitted tile from the tile processing device, output compressed image data including the encoded bit stream, receive the compressed image data, decode the compressed image data to generate a plurality of decoded code blocks, and output decompressed image data including the plurality of decoded code blocks. The scalable tile processing device receives the tile including tile image data, wavelet transforms, quantizes, segments, and encodes the tile image data to generate a plurality of encoded code blocks, and transmits an encoded bit stream including the plurality of encoded code blocks to the system.

Image processing systems employing image compression and accelerated decompression

Image processing systems employing image compression and accelerated image decompression

Growing community of inventors

Dayton, OH, United States of America

David Walker