Pmc-sierra, Inc.

David Walden Wong

Thomas Alexander

Charles Kevin Huscroft

Vernon Robert Little

Salman Ghufran

Winston K Mok

Steven F Lang

Stephen Julien Dabecki

John Richard Bradshaw

James Robert Hamstra

Richard Cam

Sivakumar Radhakrishnan

Kenneth M Buckland

Chris E Lee

Rick G Dorbolo

James Whitney Kimbrow

Riccardo G Dorbolo

Chris Edward Lee

A method of interfacing for packet and cell transfer between a first layer device and a second layer device, which includes dividing control information into an in-band portion and an out-of-band portion, transmitting the in-band portion in the data path, and transmitting the out-of-band portion outside of the data path.

System interface for cell and/or packet transfer

The present invention is a SONET payload processing system capable of handling virtual concatenation of SONET payloads. The payload processing system enables combinations of sub-frames, comprising an arbitrary number of virtual concatenation data streams, to be multiplexed into a single SONET frame stream. The present invention further provides a processing system that is not limited by the number of sub-frames or the grouping arrangement. The payload processing system accepts both virtual concatenation and contiguous concatenation within the same SONET frame stream and processes them into blocks of data that do not intermix information from different channels.

Efficient virtual concatenation datapath for SONET/SDH

The present invention provides a multiplexed payload system for processing data organized in any interleaved framing structure, preferably SONET. Along a receive path, the system consists of an input shift register, an input multi-stream merge network, a time-sliced processing unit, and a context memory. Similarly, along a transmit path, the system consists of an output shift register, an output multi-stream merge network, a time-sliced processing unit, and a context memory. The transmit path functions in an identical manner to the receive path but in the reverse direction. The multi-stream merge network, in either direction, converts between spatially separated input data streams of various configurable widths and time-division-multiplexed streams of constant width. The input shift register and the output shift register serve to accept a serial stream of bytes from the data receiver and convert them to a parallel stream of bytes presented to the input multi-stream merge network, or to accept a parallel stream of bytes from the output multi-stream merge network and convert them to a serial stream of bytes to the data transmitter, respectively. The context memory stores the processing contexts for sub-rate payload streams derived from the serial stream of bytes. A separate context memory location is assigned to each sub-rate payload stream that is received or transmitted. The time-sliced processing unit retrieves processing contexts from the context memory in a fixed sequence and uses the processing contexts to process data presented by the input multi-stream merge network, or generate data presented to the output multi-stream merge network.

Efficient variably-channelized SONET multiplexer and payload mapper

A FIFO buffer arrangement is disclosed that is capable of buffering and transferring data between multiple input and output datapaths of varying widths. All of the input and output buses may be used to transfer data concurrently. Data that are written to the FIFO via any of the input buses may be extracted from the FIFO via any of the output buses. The FIFO efficiently carries out all necessary width conversions when performing the data transfers.

Flexible FIFO system for interfacing between datapaths of variable length

An ATM layer device for interfacing between a physical layer device and an ATM switch, which includes means for prepending and postpending of switch routing information to cells destined to enter the switch and for removing such information from cells having left the switch

ATM layer device

A variable bit rate scheduler for ATM traffic shaping which includes a service rate queue (SRQ) counter for generating a base traffic profile for the control of data transmission on a virtual channel, a virtual channel peak cell rate determinator coupled to said SRQ counter and operative to determine a virtual channel peak cell sub-rate, VC.sub.-- PCR, a leaky bucket having an input for receiving sub-tokens and an output for discharging tokens and means for adding sub-tokens at the virtual channel peak cell rate to the leaky bucket and, when a cell is to be transmitted, removing a number of tokens from the bucket equal to the ratio of a virtual channel sustainable cell rate. The virtual channel sustainable cell rate is a fraction of or equal to the virtual channel peak cell rate.

Variable bit rate scheduler

An ATM network interface comprising a physical layer interface having transmit and receive line interfaces, transmit and receive framers and overhead processors coupled to respective ones of the transmit and receive line interfaces and transmit and receive cell processors coupled to respective ones of transmit and receive framers and overhead processors. The interface further includes a segmentation and reassembly interface coupled to the physical layer interface having transmit and receive ATM and adaptation layer processors coupled to respective ones of the transmit and receive ATM cell processors and a transmit ATM Traffic Shaper coupled to said Transmit ATM and Adaptation Layer Processor, and a coupler to couple the segmentation and reassembly interface to a PCI bus. By incorporating the SAR unit on the same monolithic device as the remainder of the interface, one is able to eliminate the need for expensive external static RAM or SRAM for connection context memory.

Combination local ATM segmentation and reassembly and physical layer

An available bit rate scheduling method and apparatus for asynchronous transfer mode communication of a plurality of cells over a network characterized by a system clock frequency f and an allowed cell rate ACR. Each cell belongs to an assigned virtual circuit communication channel which is defined by a set of negotiated traffic parameters. The invention partitions the ACR's of the virtual circuits into a smaller subset of profiles/sub-profiles and conducts a deterministic search to service them. The scheduler incorporates a profile generator for iteratively generating a number p of the profiles by (i) outputting a k*modulo 2.sup.i th one of the profiles during each kth iteration of the profile generator, where 1.ltoreq.i.ltoreq.p and 1.ltoreq.k.ltoreq.p-1; (ii) outputting a null profile during each 2.sup.p th one of the iterations; and, (iii) dispatching the profiles from the profile generator to the profile queue such that a particular profile is dispatched at a time T=T.sub.0 +(1/ACR)*f, where T.sub.0 is the dispatch time of a profile dispatched immediately prior to the particular profile. A profile queue coupled to the profile generator receives and sequentially stores the generated profiles. A virtual circuit processor sequentially receives the profiles from the profile queue and, for each one of the received profiles, dispatches to an output queue all virtual circuits which are characterized by the one received profile.

Available bit rate scheduler

A method of determining an error level of a data channel comprised of (a) receiving channel parity error data indicating when bit errors occur within a set of data carried on the channel (channel error events), successively integrating the channel error events data over successive accumulation periods, comparing the integrated channel error events data with a threshold, and indicating an alarm in the event the integrated channel error events data exceeds the threshold.

Programmable jump window for sonet compliant bit error monitoring

A method of interfacing between a non-continuous stream of cells of data and a continuous stream of frames of data, which includes transforming an incoming non-continuous cell stream into a continuous transmitted stream by inserting idle or non-assigned cells into the data stream during idle periods. The cells in the continuous stream are then mapped sequentially and contiguously onto the payload portions of frames. The frames are then transmitted synchronously.

Growing community of inventors

Vancouver, Canada

David Walden Wong