Hewlett-Packard Company

David W Yen

Bantwal R Rau

Ross A Towle

Wei-Chen Yen

A parallel processor computer system. The computer includes parallel processor units, an instruction unit which provides instructions to the processors and generates input and output address offsets, an invariant address unit which combines a multiconnect pointer with the address offsets to generate input and output operand addresses, and a multiconnect storage unit. Storage elements in the multiconnect unit are arranged in a matrix such that an output operand from a processor is stored in all the elements of an associated row and an input operand for a processor is obtained from any element of an associated column.

Horizontal computer having register multiconnect for operand address

A horizontal computer for execution of an instruction loop with a branch. The computer includes parallel processors, a multiconnect unit for storing operands for the processors, and instruction unit for specifying address offsets and operations to be performed by the processors, and an invariant address unit for combining the address offsets with a modifiable pointer to form source and destination addresses in the multiconnect unit. The instruction unit enables different ones of the processors both as a function of whether a branch instruction is to be executed and as a function of which iteration of the loop is being executed. The processors are enabled by processor control circuitry or by selectively providing instructions to the processors so that different operations are performed during different iterations.

Horizontal computer having register multiconnect for execution of a loop

A horizontal architecture computer in which a plurality of instructions are selectively communicated to a processing unit simultaneously or sequentially. The computer includes a processing unit with a plurality of processors, an instruction unit with a plurality of storage locations for storing instructions, and means for communicating the instructions to the processors. A first connection circuit provides a plurality of parallel communication channels between the storage locations and the processors and a second connection circuit provides a single serial communication channel between the storage locations and the processors. The first circuit is selected if a multioperation instruction is to be executed, otherwise the second circuit is selected instead.

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Cupertino, CA, United States of America

David W Yen