Advanced Micro Devices Corporation

International Business Machines Corporation

David W Wu

Scott Luning

Dong-Hyuk Ju

Emi Ishida

Khanh Q Tran

Suhong Ma

A computer-implemented method, apparatus, and computer program product in a data processing environment for transmitting information between a CORBA application executing within a client and a server utilizing HTTP are disclosed. An application that is being executed by a client requests a CORBA IDL stub to invoke a method. The CORBA IDL stub transmits requests to a server utilizing Internet Inter-ORB Protocol (IIOP). An HTTP stub is generated that transmits requests utilizing HTTP. The HTTP stub corresponds to the CORBA IDL stub such that the CORBA IDL stub and the HTTP stub define the same methods. The HTTP stub transmits the request of the CORBA IDL stub to invoke the method to the server utilizing HTTP.

Computer-implemented method, apparatus, and computer program product for transmitting information between CORBA applications and servers utilizing HTTP

The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming sub-spacers of a low dielectric constant (K) material at the corners of the gate electrode above the source/drain regions. Subsequently, insulating sidewall spacers are formed over the sub-spacers to shield-shallow source/drain regions from subsequent impurity implantations. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.

Low-K sub spacer pocket formation for gate capacitance reduction

A semiconductor device is provided with a gate electrode having a substantially rectangular profile by forming a dielectric film prior to depositing the gate electrode layer. The dielectric film is patterned and etched to form regions having a rectangular profile separated by open regions. A gate electrode layer is then deposited followed by planarization to form gate electrodes having a substantially rectangular profile.

Method of manufacturing semiconductor devices having uniform, fully doped gate electrodes

A semiconductor device is provided with a gate electrode having a substantially rectangular profile by depositing a layer of amorphous or microcrystalline silicon. The amorphous or microcrystalline silicon is doped with impurities, before patterning to form the gate electrode, to reduce gate depletion. The doped gate electrode layer is then patterned to form a gate electrode having a substantially rectangular profile.

Semiconductor device and method of manufacturing a semiconductor device having an improved gate electrode profile

A CMOS semiconductor device is formed having an N-channel transistor comprising a source/drain region and an N-LDD region with a graded junction. The graded N-LDD junction is obtained by implanting a high diffusivity N-type impurity, such as P, after the N-LDD implant, e.g., As, subsequent to sidewall spacer formation. Upon activation annealing to form the N-channel transistor source/drain regions, P diffuses to a greater depth than As, thereby forming a deeper and graded N-LDD junction.

CMOS semiconductor device comprising graded N-LDD junctions with

A CMOS semiconductor device is formed having an N-channel transistor comprising a drain region with a graded N-LDD junction. The graded N-LDD junction is obtained by plural ion implantations at different implantation dosages, energies and angles. The graded N-LDD junction reduces the electric field around the drain, thereby increasing the HCI lifetime without adversely impacting the short channel effect.

Method of forming semiconductor device comprising a drain region with a

A CMOS semiconductor device is formed having an N-channel transistor comprising a graded junction with reduced junction capacitance. The graded junction is achieved by forming a second sidewall spacer on the gate electrode, after source/drain implantations, and ion-implanting an N-type impurity with high diffusivity, e.g., P into an A.sub.5 implant, followed by activation annealing.

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San Jose, CA, United States of America

David W Wu