Texas Instruments Corporation

Interplex Nas, Inc.

David W West

Donald Charles Abbott

Christopher M Sullivan

Harold T Kelleher

Raymond A Frechette

Robert A Sabo

Robert M Fritzsche

Steve Smith

John E Cotugno

George A Dainis, Iii

Christopher Machado

A metal processing method includes etching to remove material from a thin metal part. A pattern of etch resistant material is used to prevent etching of the metal in desired locations. The etch resistant material is intentionally applied to unclean surfaces so that an adhesion between the etch resistant material and the metal will fail during the etching process. An edge is formed during etching at the boundaries of the pattern of the etch resistant material. These edges are rounded where the adhesion fails. A shaver foil is produced using the described metal processing method including a face side, a cutter side and a plurality of whisker holes. A face edge is formed where an etched profile of the whisker hole meets the face side and a cutter edge is formed where the etched profile of the whisker hole meets the cutter side. The face edge is rounded using the aforementioned process and the cutter edge is sharp using a conventional etch resistant material application method.

Method for forming an etched soft edge metal foil and the product thereof

A method for the fabrication of a double-sided electrical interconnection flexible circuit () particularly useful as a substrate for an area array integrated circuit package. A copper matrix with studs () is pressed through a dielectric film () having a copper layer on the opposite surface, thereby forming an intermediate structure for a flex circuit with self-aligned solid copper vias in a one step process. The contacts are reinforced by plating both surfaces with a layer of copper, and conventional processes are used to complete the circuit patterning.

Method of fabricating flexible circuits for integrated circuit interconnections

A double sided electrical connection flexible circuit particularly useful as a substrate for an area array integrated package, and the method of fabricating the structure is described. A circuit having interconnections on one surface and solder ball contact pads on the second surface are interconnected by copper plated from a single surface in order to avoid entrapment of air pockets. In one embodiment, the conductive vias are formed from a copper film which extends from the solder ball contact pads, which may be indented, providing a well for solder balls in the contact pad.

Flex circuit substrate for an integrated circuit package

A method of fabricating an electrically conductive via in a substrate which includes providing an electrically insulating substrate having first and second opposing surfaces and forming a first layer of electrically conductive material on the first of the opposing surfaces and forming a second layer of electrically conductive material on the second of the opposing surface. In accordance with one embodiment, the second layer has a thickness greater than the electrically insulating layer and no greater than the sum of the thicknesses of the electrically insulating layer and the first layer. In accordance with a second embodiment, the second layer has a thickness greater than the electrically insulating layer and no greater than the sum of the thicknesses of the electrically insulating layer and the first layer. A hole is formed in the first layer having sidewalls. A stud is formed in the second layer aligned with the hole in the first layer. The stud is forced through the substrate and into contact with the sidewalls of the hole. The stud preferably has a cross section to provide a friction fit with the sidewalls of the hole. In accordance with the second embodiment, the stud will extend beyond the bottom side of the polyimide layer to provide the effect of a ball from a ball grid array. The substrate can be heated to a thermoplastic state prior to forcing the stud through the substrate, if necessary. The substrate is preferably a polyimide and the electrically conductive material is preferably taken from the class consisting of copper and copper-based materials.

Method of making chip size package substrate

A leadframe (10) for diverting current to an adjacent conductor (55) when a current in the leadframe (10) exceeds a predetermined level includes a first portion (12) for carrying a chip (13) in which an integrated circuit has been constructed. A second portion (20) is connected to receive a current that flows through at least a portion of the integrated circuit. The second portion (20), which may include a bimetallic portion (40,41), is physically deformed by the current and is located to contact the adjacent conductor (55) when the current reaches the predetermined magnitude.

Deformable leadframe for overcurrent protection

A method and apparatus for forming lead frames and eliminating irregularities in the edge (22) of openings etched in the sheet metal from which the lead frame is formed. In a first process, a photo resist coated metal sheet (36) is first etched by a photo chemical process to define the lead frame, and then the lead frame metal sheet (36) is etched in an electrochemical process to remove edge irregularities. In a second process, the entire lead frame is formed in an electrochemical process.

Electrochemical etch system and method

This invention relates to a process for strengthening the adhesive bond between a lead frame and a plastic mold compound (350). The process involves plating the lead frame with a copper strike and selectively exposing the copper strike to an oxidizing agent to form a layer of cupric oxide (CuO) (318). Such lead frames are fitted with chips (324) and then encapsulated in the plastic mold compound (350), whereby the adhesive bond forms directly between the layer of CuO (318) and the plastic mold compound (350). A lead frame produced by this process may include a plurality of leads (310) having lead ends (312) and lead fingers (314) and a die pad (320) having a layer of CuO (318). The die pad (320) is encased by a plastic mold compound (350) which forms an adhesive bond directly with the layer of CuO (318). This layer (318) may have a thickness in a range of about 5 to 50.mu. inches (12.7 to 127 .mu.cm). Lead ends (312 ) and lead fingers (314) may be spot-plated with silver or palladium.

Method of forming lead frame with strengthened encapsulation adhesion

A method of making an integrated circuit (IC) device comprises the steps of providing (300) at least one lead frame (10) comprising a plurality of leads (14), laminating (302) the lead frame (10) with a photoresist, exposing (304) a portion of the photoresist to impose a pattern on the photoresist (10), and developing (306) the photoresist on lead frame (10), such that the photoresist produces a pair of strips and forms non-electrically conductive bonds (30, 32) between leads (14). Further, an IC device comprises a plurality of leads (14) extending from a lead frame (10). The leads (14) comprise an inner lead portion (26), a middle lead portion (27) and an outer lead portion (28). A photoresist is overlaid onto the leads (14). The photoresist comprises an inner strip (30) disposed across the plurality of leads (14) between the inner lead portion (26) and the middle lead portion (27) and an outer strip (32 ) disposed across the plurality of leads (14) between the outer lead portion (28) and the middle lead portion (27). The photoresist inhibits cavity molding (42) plastic from seeping onto inner lead portion (26) or outer lead portion (28) and creates a non-electrically conductive bond between the leads (14).

Integrated circuit device and manufacturing method using photoresist

A method of providing selective silver plating to a lead frame structure 10 performs the silver plating operation prior to etching the lead frame, thereby avoiding mechanical damage to the lead frame during plating, and producing finished silver spots 24 on the top surface of the lead frame only, with no plating on the gauge. The disclosed method includes the steps of applying a layer of photoresist 42 to a surface of a sheet of lead frame material 40, exposing areas of the photoresist such as to define selected regions 44, developing the photoresist 42 to uncover the lead frame material 40 at the selected regions 44, and plating the surface of the sheet defined by the layer of photoresist 42 with an electrically conductive material 46. The method further includes subsequent steps of stripping the layer of photoresist 42 from the surface, applying a layer of a second photoresist 50 to the plated surface, exposing areas of the second layer of photoresist 50 such as to define an unexposed lead frame pattern, the selected regions 44 corresponding to electrical contact locations on the lead frame pattern, and developing the photoresist 50 to uncover exposed regions 52 of the sheet of lead frame material 40. The method includes a final step of etching the sheet 40 to remove material from regions 52 uncovered by the second photoresist layer 50.

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Pembroke, MA, United States of America

David W West