Lsi Corporation

Lsi Logic Corporation

David W Vinke

Ekambaram Balaji

Bret Alan Oeltjen

Michael Norris Dillon

William Shen

Thomas Mathews Antisseril

Cristian Teodor Crisan

Nicholas A Oleksinski

Balaji Ganesan

Thai-Minh Nguyen

Christopher Coleman

Giuseppe Fornaciari

Uday Anumalachetty

An integrated circuit structure for distributing power to one or more standard cells in an integrated circuit includes a first plurality of standard cells and a power mesh power connection structure coupled to the cells. Each of the standard cells includes first and second power rails adapted for connection to a voltage supply and a voltage return, respectively, of the standard cells. Each standard cell in a subset of the standard cells is arranged in direct abutment with at least two other standard cells, and at least first and second end cells are arranged in direct abutment with at least one other standard cell of the first plurality of standard cells. The power mesh power connection structure includes a plurality of conductive elements formed in a plurality of different conductive layers in the integrated circuit. The power mesh power connection structure is operative to connect the first and second power rails of the first plurality of standard cells to the voltage supply and voltage return, respectively, and is configured so as to reduce a first voltage differential between respective first power rails of the standard cells and to reduce a second voltage differential between respective second power rails of the standard cells.

Enhanced power distribution in an integrated circuit

A method, system, and program product includes an interactive network-based site that permits a user to specify, compile, analyze and export memory configuration data associated with at least one memory component manufactured in a manufacturing environment. Such memory configuration data can be specified, compiled analyzed or exported in response to a particular user input through the interactive network-based site.

Web-enabled solutions for memory compilation to support pre-sales estimation of memory size, performance and power data for memory components

A method and apparatus are provided for generating and using timing constraints templates for IP cores that can be instantiated in an integrated circuit design. The templates include a plurality of timing constraint statements for inputs and outputs of the respective IP core. At least one of the statements includes a configurable variable, wherein the timing constraints template is configurable through the variable for each of a plurality of instances of the IP core in the integrated circuit design.

Generic methodology to support chip level integration of IP core instance constraints in integrated circuits

A clock pulse controller includes a test clock pulse input for receiving test clock pulses. A scan enable input receives a scan enable signal having a first state and a second state. A trigger pulse input receives a trigger pulse. A clock pulse output generates a launch clock pulse and a capture clock pulse from the test clock pulses immediately after receiving a predetermined number of the test clock pulses immediately following the trigger pulse. A delayed scan enable output generates a delayed scan enable signal that transitions from the first state to the second state between a leading edge of the launch clock pulse and a leading edge of the capture clock pulse.

On-chip circuit for transition delay fault test pattern generation with launch off shift

A disclosed memory, such as a random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an input node coupled to the first bit line, an enable node coupled to receive a first enable signal, and an output node coupled to a tri-state output bit line. A second tri-state buffer has an input node coupled to the second bit line, an enable node coupled to receive a second enable signal, and an output node coupled to the tri-state output bit line. Enable signal generation logic uses a portion of an address signal to generate the first and second enable signals. The memory produces an output signal dependent upon the enable signal generation logic output, and thus upon a logic level of the tri-state output bit line.

Latch-based random access memory (LBRAM) tri-state banking architecture

A disclosed memory, such as a random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an input node coupled to the first bit line, an enable node coupled to receive a first enable signal, and an output node coupled to a tri-state bit line. A second tri-state buffer has an input node coupled to the second bit line, an enable node coupled to receive a second enable signal, and an output node coupled to the tri-state bit line. Enable signal generation logic uses a portion of an address signal to generate the first and second enable signals such that the first and second enable signals are not in an active state simultaneously. Avoiding concurrent activity of the enable signals eliminates contention on the tri-state output bit lines, and thereby prevents the mutually coupled tri-state bit lines output from the first and second tri-state buffers from being active at the same time. Placing a delay between activity minimizes contention on the mutually coupled, buffered bit line.

Latch-based random access memory (LBRAM) with tri-state banking and contention avoidance

A method and apparatus for testing latch based random access memory includes steps of generating a scan enable signal for testing latch based random access memory and generating a scan clock signal for testing the latch based random access memory wherein the scan clock signal has a first scan clock period for a shift cycle and a second scan clock period for a capture cycle.

Method and apparatus for high speed testing of latch based random access memory

A latch based random access memory includes an input data register; an input data buffer coupled to the input data register; a latch array coupled to the input data buffer; and a latch array bypass multiplexer for selecting one of the input data buffer and the latch array in response to a memory scan mode signal to generate a first data output of the latch based random access memory from the input data buffer during logic scan testing and a second data output of the latch based random access memory from the latch array during memory scan testing.

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Clackamas, OR, United States of America

David W Vinke