Nxp Usa, Inc.

Motorola Corporation

International Business Machines Corporation

Freescale Semiconductor,inc.

David W Todd

Michael D Snyder

Michael Julio Garcia

Brian Keith Reynolds

Robert Alan Cargnoni

Bryan D Marietta

Jose Melanio Nunez

Joseph Gergen

Michael Scott Allen

Prabhjot Singh

Nir Atzmon

Brad B Beavers

Craig C Hunter

Nir Baruch

Mohit Satsangi

Tommi Jorma Mikael Jokinen

Benjamin Charles Eckermann

David Schuchmann

Jen-Tian Yen

Alexandru Marginean

Matthew Joseph Taylor

Iftekhar Ahmed

James E Innis

David C Holloway

A host data processing system method, apparatus, and architecture are provided for sharing a PCIe EP device with one or more lendee data processing systems in a PCIe cluster by extracting an RID value from a received PCIe transaction message corresponding to a PCIe function at the PCIe endpoint device, and then processing the RID value to identify an interconnect target port value which corresponds to a first lendee data processing system which is sharing the PCIe endpoint device, and then routing the PCIe transaction message through an interconnect on the host data processing system using an interconnect target output port corresponding to the first interconnect target port value to deliver the PCIe transaction message to the first lendee data processing system.

ID-based transaction routing for PCIe endpoint lending

A memory management component arranged to receive memory access transactions and provide memory management functionality therefor, and a method of providing memory management functionality within a processing system are disclosed. The memory management component comprises a first memory management module arranged to provide memory management functionality for received memory access transactions in accordance with a paging memory management scheme, and at least one further memory management module arranged to provide memory management functionality for received memory access transactions in accordance with an address range memory management scheme.

Memory management component having multiple memory management modules and method therefor

A system and methods controlling wake events in a data processing system is described. A broadcast wake-up signal staggering order is determined in response to a first wake event. A staggered broadcast wake-up signal is distributed to a plurality of processing elements based on the broadcast wake-up signal staggering order. The broadcast wake-up signal staggering order is changed in response to a second wake event. And a changed staggered broadcast wake-up signal is distributed to a plurality of processing elements based on the changed broadcast wake-up signal staggering order.

Method and apparatus for controlling wake events in a data processing system

A device for controlling data communication flow to a data buffer of an integrated circuit is disclosed. The device receives data communicated from a transmitting device. The received data is placed in a data buffer in memory. The data buffer is defined by a set of buffer descriptors, whereby a number of free buffer descriptors in the set of buffer descriptors is indicative of the amount of free space in the data buffer. A communications controller determines whether the data buffer is subject to overflowing by determining when the number of free buffer descriptors moves below a threshold level (a watermark). The communications controller sends a request to the transmitting device to stop transmitting data in response to determining that the data buffer is possibly subject to an overflow condition, indicating that the data buffer is nearly full.

Data communication flow control device and methods thereof

A bus protocol for a split bus (,) where each device (,) coupled to the bus has an age-based queue (,) of pending transactions. Queues are updated as transactions are executed. A central arbiter (,) has a copy of each device's queue (,). A priority transaction is determined from among all the queues in the arbiter. A data transaction index (DTI) is broadcast during the data tenure to all devices indicating the position in the queue of the next transaction. The index allows out-of-order data transfers without the provision of a static tag during the address tenure. Queues maintain a history of pending transactions. In one embodiment, each device receives a separate data bus grant (DBG), allowing a single provision of the index to both a source and a sink device.

Method and apparatus for transferring data on a split bus in a data processing system

A method of transferring data between a slave device (20) in communication with a processor interface bus (34) where the processor interface bus is in communication with a master device (12) including receiving an address from the processor interface bus (34) where the address was provided by the master device (block 302). A first signal is asserted (blocks 318 and 324) on the processor interface bus (34) to indicate that the slave device (20) is servicing a data transfer transaction. A second signal is asserted (block 320) on the processor interface bus (34) to indicate whether data to be transferred using the processor interface bus (34) is to be stored in main memory (36) by a main memory controller (32) in communication with the processor interface bus (34). The data is transferred (block 326) between the slave device (20) and the processor interface bus (34).

Method and apparatus for transferring data over a processor interface bus

The present invention provides a system and method for efficient execution of load reserve (LARX) and store conditional (STCX) instructions in a superscalar processor. A system for efficiently providing a LARX instruction in a superscalar processor is disclosed. The system comprises a data cache (Dcache) for receiving the LARX instruction. The data cache further includes a decoder means for setting and resetting of a validation of the load reserve instruction, an internal cache for receiving address information and for providing data. The system also includes a register means for receiving the LARX instruction and a controller means for providing a physical address based upon the address information. The system provides for the validation being accomplished in one cycle for the LARX instruction when there is a hit on the internal data cache.

High performance implementation of the load reserve instruction in a

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Austin, TX, United States of America

David W Todd