Advanced Micro Devices Corporation

David W Stoenner

Sherman E Lee

William M Johnson

Drew Jon Dutton

Timothy A Olson

Percy R Aria

An input/output (I/O) buffer is presented which selectively provides resistive termination for a transmission line coupled to an input/output node. The I/O buffer includes the input/output node, a first output driver stage, a second output driver stage, a differential amplifier, and an input termination stage. The first output driver stage is enabled when resistive termination of the transmission line is not required (e.g., when an older bus standard is to be supported). The second output driver stage is enabled when resistive termination of the transmission line is required (e.g., when a higher performance bus is to be supported). The differential amplifier produces a logic high input signal when a voltage driven upon the input/output node by the transmission line is greater than a reference voltage, and produces a logic low input signal at the output terminal when the voltage driven upon the input/output node by the transmission line is less than the reference voltage. In one embodiment, the input termination stage includes a termination node, a resistive element coupled between the input/output node and the termination node, and a time delay unit. The time delay unit receives the input signal produced by the differential amplifier and produces a time-delayed input signal after a predetermined time delay has elapsed. The termination node is selectively coupled to either the power supply potential or the ground potential dependent upon the time-delayed input signal produced by the time delay unit.

Input/output (I/O) buffer selectively providing resistive termination

Methods and apparatus are disclosed for transferring data to and from the Local Bus of a reduced instruction set computer (RISC) system, to which a first set of high performance devices, including at least one central processor ('CPU'), is attached, and a Remote Bus, to which a second set of relatively lower performance devices is attached, in a manner that does not limit the RISC processor's performance. According to the preferred embodiment of the invention, a RISC architecture is disclosed that includes a novel data transfer controller ('DTC'), or set of DTCs, suitable for performing the aforesaid data transfer function between the high performance Local Bus and one or more Remote Buses to which complete subsystems or peripherals, typically having different (and lower) performance characteristics, are attached. The resulting RISC arthitecture permits commercially available peripherals and subsystems to be used with high performance RISC processors without limiting RISC system performance.

Reduced instruction set computer system including apparatus and method

Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ('CPU') is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the above transfer function in a manner that facilitates communication between the first and second set of devices from the compartively lower performance of the second set of devices. According to the preferred embodiment of the invention, a data transfer controller i.e., ('DTC') is disclosed that includes a set of direct memory access ('DMA') channels and an input/output controller comprising a set of address mapped I/O ports. Both the DMA channels and I/O ports may be used to transfer data between the high performance channel (hereinafter referred to as the 'Local Bus') coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a 'Remote Bus'). The resulting DTC interface between the Local Bus and a Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance.

Data transfer controller incorporating direct memory access channels and

A data processing system having a processor capable of initiating a request for a burst of data transfer and a memory. A memory controller is connected to the processor and to the memory. The controller includes a burst count register having a value stored therein representative of the maximum number of data transfers allowed per burst. Also in the memory controller is a column latch/counter having stored therein a value representative of a column latch address. The column latch/counter is capable of incrementing the address. Finally, included in the memory controller is a programmable mask for specifying bits in the column latch/counter to be compared to corresponding bits in the burst count register.

Programmable burst data transfer apparatus and technique

Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ('CPU') is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the transfer function in a manner that facilitates communication between the first and second set of devices from the comparatively lower performance of the second set of devices. Direct memory access ('DMA') apparatus and methods are disclosed, including a set of direct memory access channels. The DMA channels may be used to transfer data between the high performance channel (hereinafter referred to as the 'Local Bus') coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a 'Remote Bus'). The resulting DMA interface between the Local Bus and a Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance. The noval DMA may also be used as part of a data transfer controller (DTC) having other components, such as I/O ports, or may be used independently for transferring data between unmatched buses in, for example, computer systems, data transmission systems and the like.

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El Toro, CA, United States of America

David W Stoenner