Cypress Semiconductor Corporation

David W Still

Jayant Ashokkumar

James D Allan

Joseph S Tandingan

Helmut Puchner

Suhail Zain

Jesse J Siman

Walt Anderson

David Gordon Wright

Jaskarn Singh Johal

Judith E Allen

Andreas Scade

Jay Ashokkumar

John Roger Gill

Srikanth Reddy Tiyyagura

Srikanth—Reddy Tiyyagura

James Allen

A memory including an array of nvRAM cells and method of operating the same, where each nvRAM cell includes a volatile charge storage circuit, and a nonvolatile charge storage circuit including a solitary non-volatile memory (NVM) device, a first transistor coupled to the NVM device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM device through which a compliment of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM device is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM device, the second transistor is coupled to a second node of the NVM device and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.

10-transistor non-volatile static random-access memory using a single non-volatile memory element and method of operation thereof

A memory including an array of nvSRAM cells and method of operating the same are provided. Each nvSRAM cell includes a volatile charge storage circuit, and a non-volatile charge storage circuit including exactly one non-volatile memory (NVM) element, a first transistor coupled to the NVM element through which data true is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM element through which a complement of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM element is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM element, the second transistor is coupled to a second node of the NVM element and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.

Multi-bit non-volatile random access memory cells are disclosed. A multi-bit non-volatile random access memory cell may include a volatile storage element and a non-volatile storage circuit. The non-volatile storage circuit may include at least one first pass transistor connected to a data true (DT) node of the volatile storage element and at least one second pass transistor connected to a data complement (DC) node of the volatile storage element. The non-volatile storage circuit may also include multiple non-volatile storage elements. Each non-volatile storage element may be configured to be selectively connectable to the DT node of the volatile storage element via the at least one first pass transistor and selectively connectable to the DC node of the volatile storage element via the at least one second pass transistor, allowing the multi-bit non-volatile random access memory cell to store/recall more than one databit per cell.

Multi-bit non-volatile random-access memory cells

A memory cell includes a storage element coupled to a first data node and a second data node, a first programmable nonvolatile element and a second programmable nonvolatile element, a first switch element and a second switch element. The first switch element is configured to couple the first programmable nonvolatile element to the first data node during a first read mode of the memory cell. The second switch element is configured to couple the second programmable nonvolatile element to the second data node during the first read mode.

High reliability non-volatile static random access memory devices, methods and systems

A device is configured to establish first and second device power domains. Isolation circuits isolate signals from passing between circuits in the first device power domain and circuits in the second device power domain. During a transition between power domains, an n-bit value is stored in a particular storage location, and compared to a particular n-bit value. Isolation between the first and second device power domains is removed when the n-bit value stored in the particular storage location matches the particular n-bit value.

Device and method of establishing sleep mode architecture for NVSRAMs

A device can include a plurality of memory cells, each memory cell including at least one latch circuit coupled between two data nodes, a first nonvolatile section coupled to a first data node, and a second nonvolatile section coupled to a second data node; and each nonvolatile section including at least one switch element in series with a programmable nonvolatile element, the switch element configured to couple the nonvolatile element to the corresponding data node during a high reliability read operation of the memory cell.

A memory circuit includes a controlled current source coupled to an input to a nonvolatile cell, and a second controlled current source coupled to a volatile cell, the volatile cell coupled to receive current from the controlled current source via the nonvolatile cell.

Current controlled recall schema

A verification circuit for a capacitor power supply measures at least two voltages across the terminals of the capacitor at two points in time, the two points in time defining a time interval dT. A change in voltage dV over the time interval dT is determined. An operation powered by the capacitor is initiated, or not, by deriving from the time interval dT and/or the voltage change dV, a total required time or a total required voltage for completing the operation, and comparing the total required time or total required voltage to a pre-determined necessary total time or predetermined necessary total voltage, respectively (a 'time interval test').

Capacitor power source tamper protection and reliability test

A semiconductor memory array having a first memory cell array with a number of first memory cells and a second cell array with a number of second memory cells. The memory cells in the first and second memory cell arrays are arranged in rows and columns. Each column of second memory cells in the second memory array is coupled to a column of first memory cells in the first memory array.

Combination SRAM and NVSRAM semiconductor memory array

A system and method for programming and erasing a semiconductor memory is disclosed. More particularly, the present invention uses the bit lines of a volatile memory portion of semiconductor memory so as to program and erase the non-volatile portion of the semiconductor memory.

Method and apparatus to program and erase a non-volatile static random access memory from the bit lines

A system and method for programming both sides of the non-volatile portion in a semiconductor memory is disclosed. The present invention erases and then programs the memory stacks in the non-volatile portion of an nvSRAM.

Method and apparatus to program both sides of a non-volatile static random access memory

A system and method for disturbing an erased memory location structure in a non-volatile portion of a semiconductor memory is disclosed. The present invention applies a voltage to a first memory location of a non-volatile portion of the semiconductor memory that is in a programmed state and a second memory location of a non-volatile portion of the semiconductor memory that is in an erased state so as to keep the first memory location programmed and to transition the second memory location from a programmed state to an erased state.

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Colorado Springs, CO, United States of America

David W Still