International Business Machines Corporation

Globalfoundries Inc.

David W Siljenberg

Steven John Baumgartner

Anthony Gus Aipperspach

Charles Porter Geer

Daniel Mark Dreps

Ronald L Soderstrom

Ladd William Freitag

Gerald M Heiling

John T Trnka

David Paul Paulsen

Todd Alan Christensen

Anthony Richard Bonaccio

Layne A Berge

Derick Gardner Behrends

Timothy Roy Block

Benjamin A Fox

Sergey Vladimirovich Rylov

Matthew James Paschal

Mounir Meghelli

George Russell Zettles, Iv

Timothy Clyde Buchholtz

Alan P Wagstaff

Wesley David Martin

Dana Marie Woeste

Dennis L Karst

John Steven Mitby

Marcia B Ebler

Spencer C Holter

Hayden C Cranford, Jr

Gregory John Uhlmann

William Paul Hovis

Phil Christopher Paone

John Francis Bulzacchelli

Salvatore Nicholas Storino

Delbert Raymond Cecchi

Michael Launsbach

John Farley Ewen

Rick Allen Philpott

Curtis Walter Preuss

Daniel Guy Young

Brian Andrew Schuelke

Raymond J Thatcher

Alan James Leslie

Daniel Scott Hedin

Stephen Charles Wilkinson-Gruber

Anh Duy Ngo

Michael J Peterson

David A Knodel

Daniel Bravo Lacap

Embodiments herein discuss tuning a testing apparatus to better match the input response of a target system in which a cable will be used. For example, conductors in the cable may have a different skew depending on the system in which they are used. The testing apparatus may be tuned using frequency information regarding the type of signals that will be driven on the cable when installed in the target system. In one embodiment, the testing apparatus adjusts a testing cycle refresh rate for generating a testing signal which changes the frequency content of the testing signal. Using the adjusted testing cycle refresh rate results in the driver outputting a testing signal that better reflects the actual signals that will be transmitted on the cable in the target system.

Tuning a testing apparatus for measuring skew

Embodiments herein discuss tuning a testing apparatus to better match the input response of a target system in which a cable will be used. For example, conductors in the cable may have a different skew depending on the system in which they are used. The testing apparatus may be tuned using frequency information regarding the type of signals that will be driven on the cable when installed in the target system. In one embodiment, the testing apparatus uses the frequency information to configure a programmable clock source that can be used to shape a reference clock and control a driver to match the signals in the target system. Using the clock source to modify the reference clock results in the driver outputting a testing signal that better reflects the actual signals that will be transmitted on the cable in the target system.

A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.

Level-shifting latch

An electrostatic discharge (ESD) protection device to manage leakage current can, in response to a power good (PGOOD) signal, draw the gate terminal of an ESD clamp device to a voltage below ground. The device also drives an inverted copy of the PGOOD signal to a gated inverter, which can inhibit the gated inverter output from drawing the ESD clamp device gate terminal to ground. The ESD protection device also includes the ESD clamp device to, in response to the gate terminal of the ESD clamp device being drawn to a bias voltage less than ground, allow a leakage current to flow through the ESD clamp device that is less than a leakage current allowed to flow in response to the ESD clamp device gate terminal being drawn to ground.

Electrostatic discharge protection device with power management

Power aware equalization in a serial communications link that includes a transmitter and a receiver, including: determining, by a power aware equalization module, a required signal eye width and a required signal eye height for signals received by the receiver; identifying one or more signal equalizers for signals transmitted over the serial communications link; identifying one or more cumulative equalizer settings that equalize signals transmitted over the serial communications link to conform with the required signal eye width and the required signal eye height for signals received by the receiver; determining power consumption values associated with each of the one or more cumulative equalizer settings; and setting the one or more signal equalizers to configuration settings in dependence upon the power consumption values associated with each of the one or more cumulative equalizer settings.

Power aware equalization in a serial communications link

A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

Architecture for a physical interface of a high speed front side bus

A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

An eFuse reference cell on a chip provides a reference voltage that is greater than a maximum voltage produced by an eFuse cell having an unblown eFuse on the chip but less than a minimum voltage produced by an eFuse cell having a blown eFuse on the chip. A reference current flows through a resistor and an unblown eFuse in the eFuse reference cell, producing the reference voltage. The reference voltage is used to create a mirrored copy of the reference current in the eFuse cell. The mirrored copy of the reference current flows through an eFuse in the eFuse cell. A comparator receives the reference voltage and the voltage produced by the eFuse cell. The comparator produces an output logic level responsive to the voltage produced by the eFuse cell compared to the reference voltage.

eFuse sense circuit

An apparatus and method is disclosed for transmitting signals over a signal conductor using a precompensated driver that does not use a current source, and which drives the signal conductor with an impedance similar to the characteristic impedance of the signal conductor. Since no current source is used, the precompensated driver can operate at very low supply voltage.

Pre-emphasis driver with constant impedance

A method and apparatus are provided for implementing power control in multi-voltage input/output (I/O) circuits. First current biasing devices are provided for creating a first constant bias current. Second current biasing devices are provided for creating a second bias current. The second current biasing devices are activated at a first voltage and are deactivated at a second voltage. The first voltage is less than the second voltage.

Method and apparatus for implementing power control in multi-voltage I/O circuits

A dual mode, analog differential and complementary metal oxide semiconductor (CMOS) logic circuit is provided. The circuit includes a differential input for receiving a differential input signal. A switch pair is coupled to the differential input. A pair of load resistors coupled to the switch pair defines a differential output for providing a differential output signal. A current source is coupled to the switch pair. A control input receives a control signal and control circuitry coupled to the control input disable the current source to select a CMOS testing mode responsive to the control signal being activated.

Dual mode analog differential and CMOS logic circuit

Method and apparatus for testing a parallel optical transceiver are provided. One embodiment provides a built-in self-testing (BIST) parallel optical transceiver comprising a full-rate clock test pattern generator and a clock divider circuit connected to provide a half-rate clock signal to one of the one or more transmitter channels, and an error detector comprising one or more error detection circuits connected to one or more receiver channels and configured to receive the half-rate clock signal. Another embodiment provides a method for testing a parallel optical transceiver, comprising: generating a full-rate clock test pattern to one or more transmitter channels; providing a half-rate clock signal to one of the one or more transmitter channels utilizing a clock divider circuit; transmitting test pattern and half-rate clock signals to one or more corresponding receiver channels; and detecting error utilizing one or more error detection circuits connected to receive the half-rate clock signal.

Architecture for built-in self-test of parallel optical transceivers

An improved laser diode driving circuit is disclosed which includes a current source, an operational amplifier, a light sensing device, a current mirror, and a constant current source. The current source is coupled to the laser diode for biasing the laser diode. The operational amplifier has an output coupled to the current source for driving the current source. The operational amplifier includes a first and a second input. The first input is coupled to a reference voltage. The second input receives a feedback signal. The light sensing device is coupled to a first supply voltage for detecting a portion of an optical power output from the laser. The light sensing device generates a monitor current proportional to the detected optical power output. The current mirror is coupled to the light sensing device and the second input of the operational amplifier. The current mirror receives the monitor current and generates a mirror current which is substantially equal to the monitor current. The constant current source is coupled to the second input of the operational amplifier for outputting a reference current. The reference current and the mirror current are then utilized to generate the feedback signal.

Laser diode driving circuit

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Byron, MN, United States of America

David W Siljenberg