Nuvotronics, LLC

Shipley Company LLC

Rohm & Haas Electronic Materials LLC

Samsung Electronics Co., Ltd.

Cubic Corporation

Bae Systems Information and Electronic Systems Integration Inc.

Rohm and Haas Electronics Materials LLC

Nuvotornics, LLC

Haleos, Inc.

Act Microdevices, Inc.

Shipley&plusmn;company, L.l.c.

David W Sherrer

Dan A Steinberg

John J Fisher

Jean-Marc Rollin

Mindaugas Fernand Dautartas

Noel A Heiks

Kenneth J Vanhille

J Robert Reid

Larry J Rasnake

Will Stacy

Ken Vanhille

Marcus Oliver

Steven Edward Huettner

William D Houck

Neal Ricks

Ian Hovey

Tim Smith

J Marcus Oliver

Donald E Leber

James MacDonald

Hui Luo

James Robert Reid

William Stacy

Arden Jeantilus

Neil Ricks

Donald X Wu

Mindaugas F Dautargas

Garo Khanarian

John P Cahalen

Matthew L Moynihan

Robert G Schinazi

Carl J Colangelo

Carl Gaebe

Shifang Zhou

Brian D Amos

Benjamin L Cannon

Timothy Amis Smith

Jasean Rasnake

Jared Williams Jordan

James R Reid, Jr

Steve Huettner

Gregory A Ten Eyck

James C Hurst, Jr

Don E Leber

Margaret M Pafford

Gregory A TenEyck

Mindaugas F Daurtartas

Kevin S Horgan

Bruno M Sicard

Mindaugus F Dautargas

Christopher A Nichols

James W Getz

Daniel L Fonataine

Dara L Cardwell

Oliver Marcus

Carl E Gaebe

Antenna arrays, including a broadband single or dual polarized, tightly coupled radiator arrays.

Broadband antenna array

A process to form devices may include forming a seed layer on and/or over a substrate, modifying a seed layer selectively, forming an image-wise mold layer on and/or over a substrate and/or electrodepositing a first material on and/or over an exposed conductive area. A process may include selectively applying a temporary patterned passivation layer on a conductive substrate, selectively forming an image-wise mold layer on and/or over a substrate, forming a first material on and/or over at least one of the exposed conductive areas and/or removing a temporary patterned passivation layer. A process may include forming a sacrificial image-wise mold layer on a substrate layer, selectively placing one or more first materials in one or more exposed portions of a substrate layer, forming one or more second materials on and/or over a substrate layer and/or removing a portion of a sacrificial image-wise mold layer.

Multilayer build processes and devices thereof

Provided are integrated electronic components which include a waveguide microstructure formed by a sequential build process and an electronic device, and methods of forming such integrated electronic components. The microstructures have particular applicability to devices for transmitting electromagnetic energy and other electronic signals.

Integrated electronic components and methods of formation thereof

Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems.

Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems

An apparatus comprising a first power combiner/divider network and a second power combiner/divider network. The first power combiner/divider network splits a first electromagnetic signal into split signals that are connectable to signal processor(s). The second power combiner/divider network combines processed signals into a second electromagnetic signal. The apparatus includes a three-dimensional coaxial microstructure.

Three-dimensional microstructures

Substrate-free mechanical structural systems comprised of interconnected subsystems of electronic and/or electromechanical components.

Substrate-free interconnected electronic mechanical structural systems

Provided are coaxial transmission line microstructures formed by a sequential build process, and methods of forming such microstructures. The microstructures include a transition structure for transitioning between the coaxial transmission line and an electrical connector. The microstructures have particular applicability to devices for transmitting electromagnetic energy and other electronic signals.

Method of forming a coaxial line microstructure having an enlarged region on a substrate and removing the coaxial line microstructure from the substrate for mounting on a mounting substrate

Provided are coaxial waveguide microstructures. The microstructures include a substrate and a coaxial waveguide disposed above the substrate. The coaxial waveguide includes: a center conductor; an outer conductor including one or more walls, spaced apart from and disposed around the center conductor; one or more dielectric support members for supporting the center conductor in contact with the center conductor and enclosed within the outer conductor; and a core volume between the center conductor and the outer conductor, wherein the core volume is under vacuum or in a gas state. Also provided are methods of forming coaxial waveguide microstructures by a sequential build process and hermetic packages which include a coaxial waveguide microstructure.

Coaxial waveguide microstructures having conductors formed by plural conductive layers

Structures, materials, and methods to control the spread of a solder material or other flowable conductive material in electronic and/or electromagnetic devices are provided.

Devices and methods for solder flow control in three-dimensional microstructures

The present invention relates to the fabrication of complicated electronic and/or mechanical structures and devices and components using homogeneous or heterogeneous 3D additive build processes. In particular the invention relates to selective metallization processes including electroless and/or electrolytic metallization.

Methods of fabricating electronic and mechanical structures

Substrate-free mechanical structural systems comprised of interconnected subsystems of electronic and/or electromechanical components are provided.

Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component.

Device package and methods for the fabrication and testing thereof

Growing community of inventors

Radford, VA, United States of America

David W Sherrer