Texas Instruments Corporation

David W Rekieta

John P Volpi

Mitchel B Stiles

Hugh L Scott

Leonard J LaPadula, Iii

Chyi H Lu

Kenneth L Williams

Rakesh N Joshi

Philip A Roden

Getzel Gonzalez Garcia

Patrick C Neil

Krunali T Patel

Jason Marc Cole

George W Pawlowski

Mark A Beadle

Getzel Gonzalez

Bradley A Little

A method of displaying an image includes alternating an active state of each of a plurality of light sources. The light sources each generate a light beam when active. The alternating includes deactivating an active light source before an output of a light beam from the active light sources falls below a first predetermined threshold. The alternating further includes activating a deactivated light source only after an output of the inactive light source reaches a second predetermined threshold. The method further includes receiving each of the light beams at a spatial light modulator.

Method and system for generating a display

According to one embodiment of the present invention, a method of displaying an image includes alternating an active state of each of a plurality of light sources. The light sources each generate a light beam when active. The alternating includes deactivating an active light source before an output of a light beam from the active light sources falls below a first predetermined threshold. The alternating further includes activating an inactive light source only after an output of the inactive light source reaches a second predetermined threshold. The method further includes receiving each of the light beams at a modulator. The modulator includes an array of micro-mirror devices.

According to one embodiment of the invention, a network system for carrying control data between a controller and a device to be controlled is provided. The network system comprises a bus system operable to carry data between the controller and the device according to an IEEE 1394 standard. The IEEE 1394 standard defines a start up operation that includes one or more sequences. The bus system is also operable to perform a modified start up operation that excludes at least one of the sequences of the start up operation defined by the IEEE 1394 standard.

Method and system for rapidly starting up an IEEE 1394 network

An asynchronous First-In-First-Out memory integrated circuit is equipped with a Built-In Self Test logic structure which allows extensive full-frequency asynchronous memory testing requiring minimal external test equipment. Memory input data patterns are generated by write data pattern circuitry responsive to a write clock signal. The write data generator considers the full status of the FIFO memory device. A read data generator provides an expected output data pattern corresponding to the data pattern provided by the write data generator responsive to a read clock signal such that the status of the FIFO memory device is taken into account. A read data error circuit compares the expected output data with the actual output data, indicating any mismatch between the two. Further this asynchronous First-In-First-Out memory device stores information regarding the nature of any mismatches and allows this information to be serially read from its output.

Asynchronous FIFO memory having built-in self test logic

A controller ( ) for coupling between a computer bus ( ) and one or more units ( ) compatible with the bus. The controller comprises a first input ( ) for receiving a first reset signal issued from the computer bus, and a second input ( ) for receiving a second reset signal. The controller further comprises circuitry ( ) for storing a first set of information which will be cleared in response to assertion of the first reset signal. Lastly, the controller comprises circuitry ( ) for storing a second set of information which will not be cleared in response to assertion of the first reset signal but which will be cleared in response to assertion of the second reset signal. In a described embodiment, the bus is a PCI bus, the first reset signal is a PCI Reset signal, and the second reset signal is an initialization signal.

Circuits, systems, and methods for efficient wake up of peripheral component interconnect controller

A power management method and system which includes providing a system having a plurality of clock operated circuits, each clock operated circuit being operable in response to the receipt of clock signals. A first subplurality of the clock operated circuits receives an uninterrupted stream of clock signals and thereby is uninterruptably operable and a second plurality of the clock operated circuits receives a normally off interruptable stream of clock signals and is normally inoperable. The system is sampled for the presence of data signals being input thereto. The clock signals are sent to the second plurality of circuits in response to the sampling the presence of data signals being input to the system to cause the second plurality of circuits to be operable. The data signals are transmitted to the second plurality of circuits after a time delay equal to or greater than the expired time from the sampling to the sending. The system can have a plurality of input/output terminals with the sampling comprising being at each of the input/output terminals. The system includes a clock for providing the clock signals and a decode logic for sampling at one of the input/output terminals and an arbiter circuit for sampling at the other input/output terminal.

Dynamic device power management

There is disclosed a multi channel GPS digital signal processor on a single IC. Each channel contains circuitry to process L1 or L2 P(Y) and C/A-code signals. In addition a search processor is included to achieve fast signal acquisition. Low power adder/accumulators have been designed to provide for a high precision digital oscillator whose output is synchronous to a high speed clock. The IC contains a full low power null detector and eight correlators to aid in signal acquisition.

Method and system for a multi channel and search global position system

There is disclosed a global positioning system receiver method and system which converts the analog signals to digital signals prior to performing signal acquisition and GPS unique processing functions. The A/D converter uses full null zone processing to increase anti-jamming capability and 4-level output to reduce signal processing. A single analog and digital channel is used for both the L1 and L2 channels as well as for all P(Y)-code and C/A-code thus allowing full multi channel tracking with several channels each tracking a separate signal while the remainder of the channels rove over all of the signals on the alternate L-band with programmable duty cycles. The system allows for Y-code substitution for P-code by multiplexing a portion of the Y-code generated between multiple channels.

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Van Alstyne, TX, United States of America

David W Rekieta