Sun Microsystems, Inc.

David W Poole

Edgardo F Klass

Chaim Nmi Amir

Alan C Rogers

Raymond A Heald

Gary R Gouldsberry

A dynamic logic signal repeater includes a complementary dynamic logic circuit with an input node to receive an input signal and an output node storing a precharge signal. The complementary dynamic logic circuit configuration, transistor sizing, and the use of a precharge driver results in a signal transition trip point for the precharge signal on the output node that is substantially equivalent to the signal transition trip point of a static logic circuit. Thus, the dynamic logic signal repeater has improved noise immunity. An evaluation locking transistor is connected to the complementary dynamic logic circuit and the output node. The evaluation locking transistor prevents the charging of the output node during a dynamic logic evaluation period.

Apparatus and method for improving the noise immunity of a dynamic logic

A non-blocking multiple-phase clocking system for use with dynamic logic provides clock phases with overlapping evaluation phases to a circuit including a several cascaded dynamic logic gates. The circuit also includes a first flip-flop that is coupled to provide input signal(s) to the first dynamic logic gate of the cascade and a second flip-flop that is coupled to receive output signal(s) from the last dynamic logic gate of the cascade. Through the use of the overlapping evaluation phases and proper assignment of the clock signals to the dynamic logic gates, the output signal(s) generated by the dynamic logic gates receiving a particular clock phase are used as input signals to the dynamic logic gates receiving the next clock phase. Because of the overlapping of the clock phases, no latch is used. The clock phases are assigned to a particular dynamic logic gate so that the this dynamic logic gate enters the evaluation phase before the input signal(s) to the particular dynamic logic gate arrives (i.e., a 'non-blocking') manner so that delay through the dynamic logic circuit can be minimized. To ensure that valid output signals are received by the dynamic logic gates receiving the next clock phase, the clock phases are assigned so that this particular dynamic logic gate receives its input signal(s) before the start of the evaluation phase of any subsequent clock phase.

Non-blocking multiple phase clocking scheme for dynamic logic

A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data put signal. The first and second input latches have first and second shutoff circuits, respectively. During a precharge phase, the first and second input latches each provide an output signal of a first logic level. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal, respectively. In response to the samples of true and the complement of the data input signal, one input latch's output signal will transition to a second logic level, while the other input latch's output signal will remain at the first logic level. A first output latch and a second output latch are coupled to receive the output signals of the first and second input latches, respectively. The first and second output latches are inverting. During the precharge phase, the flip-flop provides output signals of the second logic level from both of the output latches. During the evaluation phase, one output latch will continue to provide an output signal of the second logic level and the other output latch will provide an output signal that transitions from the second logic level to the first logic level.

Edge-triggered dual-rail dynamic flip-flop with self-shut-off mechanism

A memory array with improved access time is disclosed. In one embodiment, the memory array includes a plurality of memory cells arranged in rows and columns. Each one of the plurality of columns includes a global bit line, a local bit line with a memory cell coupled thereto, and an MOS switch configured to selectively couple the local bit line and the global bit line in response to a column select signal. In a second embodiment, the memory array includes a plurality of sense amplifiers located at the periphery of the array, and a plurality of columns associated with the plurality of sense amplifiers respectively. Each one of the plurality of columns includes a global bit line, a local bit line with a memory cell coupled thereto; and a switch coupled between the local bit line and the global bit line and configured to selectively move the global bit line in response to the contents of the memory cell during a read operation. In either embodiment, the switch is an MOS transistor having its drain coupled to the global bit line, its gate coupled to the local bit line, and its source coupled to a reference voltage. During operation, a word line coupled to the memory cell is activated at approximately the same time as the column select signal to access the memory cell. The configuration of the MOS transistor switches provides for maximum transconductance in discharging the global bit lines.

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Mountain View, CA, United States of America

David W Poole