International Business Machines Corporation

David W Nuechterlein

William Robert Lee

David Ronny Dwin

Thomas Andrew Sartorius

Kenneth D Schultz

Kim E O'Donnell

Paul Stewart Yosim

Francois Ibrahim Atallah

Joseph Michael Pennisi

Mark Anthony Rinaldi

Larry D Larsen

Stacy J Garvin

Harry I Linzer

Paul S Yosim

Lee S Rogers

William E Coyle

Emmy M Wolters

The display buffer of a multimedia workstation is partitioned into a display section and a non-display section. The information to be displayed on the display screen is arranged in the display section of the display buffer. An image or shadow of the display section is written in the non-display section (called a lock buffer) of the display buffer. Prior to updating the display section, a controller reads the protection data from the lock buffer and generates control signals which inhibit the writing of data into protected areas of the display section.

Device for protecting selected information in multi-media workstations

A programmable memory controller includes a plurality of multi-bit registers, with each multi-bit register coupled to a cycle generator. Each cycle generator is formed from a multi-bit shift register and control signals which drive each multi-bit shift register so that data in an associated multi-bit register is shifted through the shift register to form desired memory control pulses.

Programmable memory controller and data terminal equipment

An adapter for use in a multi-media workstation includes a device which accepts real-time video information at a first size, reduces the size to a selected one of a plurality of available sizes and places the reduced real-time video information into a selected area of the video memory of a computer graphic display device. Thereafter, the scaled real-time video information is displayed with other computer graphics applications, in a sub-window of the screen of the display device.

Device for scaling real-time image frames in multi-media workstations

A content addressable memory in accordance with the present invention includes a number of bistable memory cells having as inputs thereto first and second bit lines and an address line, and a COMPARE circuit connected to each of the memory cells so as to provide the COMPARE function without loading the first and second bit lines and including means for inhibiting current flow when a miscompare occurs.

Fast content addressable memory with reduced power consumption

The use of a high speed cache memory may be selectively controlled when a data processing task is interrupted in response to an interrupt signal, in order to prevent the interrupt from chilling the cache when insufficient performance enhancement will be realized. Disturbing the cache memory during performance of an interrupting task is prevented, thereby increasing the hit ratio of the cache when the interrupted task is resumed. Cache control information may be incorporated into a program status vector or program status word which is loaded into a program status register on occurrence of an interrupt.

Method and apparatus for controlling operation of a cache memory during

A reconfigurable set associative cache memory can be reconfigured from 2.sup.x way to 2.sup.y way set associative cache memory by effectively merging a predetermined number of least significant bits of the tag field of the main memory address with the line field of the main memory address. The effective merging is provided by logically merging least significant bits of the tag field with a reconfiguration designation. As a result, Y-X+1 different configurations of cache memory can be obtained using the Y-X least significant bits of the tag field merged with the cache memory address.

Reconfigurable multi-way associative cache memory

A processor adapted for parallel and/or pipelined interconnection with other like processors. An arithmetic logic unit has associated with it an output FIFO register stack having output data lines capable of parallel connection with the output data lines of other such processors, such output stack being loadable with a predetermined neutral value such that when the neutral value is present at their output data lines it permits the data present at the output lines of another such processor connected in parallel therewith to control the output data bus. The invention eliminates the need to have control over several such processors connected in parallel and/or pipelined configuration by way of external arbitration logic.

Growing community of inventors

Durham, NC, United States of America

David W Nuechterlein