Alcatel Network Systems, Inc.

David W Kuddes

Anthony J Mazzola

Scott Alan Green

Gregory J Longendyke

Cecil Mathews

A data processing system including dynamic random access memory (DRAM) in a bus architecture is disclosed. A controller is included in the system which unconditionally generates the row address strobe (RAS.sub.--) and column address strobe (CAS.sub.--) signals to the DRAM responsive to the initiation of a bus cycle. The controller also includes a decoder which decodes the address value during the DRAM cycle initiated by the RAS.sub.-- and CAS.sub.-- signals, and generates the select signals (for example, output enable and write enable signals, depending upon whether the access is a read or a write) if the address value indicates that the bus operation is to be a DRAM access. No select signal is generated in the event that the bus operation is not a DRAM access, so that the DRAM operation initiated by the RAS.sub.-- and CAS.sub.-- signals remains an internal operation and does not affect the common data bus. The effective DRAM system cycle time is reduced because all bus operations assume that the operation is a DRAM access; no DRAM access is delayed by the decoding of the address value.

System and method for fast memory access using speculative access in a

A reset pulse generating circuit is disclosed for generating reset pulses that are used for placing digital systems such as microprocessors into a known state upon power-up and when power fluctuations occur. The reset pulse generating circuit includes a memory circuitry and a counter circuitry, and is designed to work in conjunction with a threshold detector circuitry that monitors the level of the power supply voltage and provides a binary output indicating whether the power supply voltage is above or below a threshold value. The memory circuitry includes four series-connected D-type flip flops, the first two of which are resetable in response to fluctuations in the supply voltage and asynchronous to the system clock. The asynchronous reset inputs of the latter flip flops are for coupling to the output of the threshold detector circuitry. The output of the memory circuitry is used to control the counter circuitry. In turn, the counter circuitry provides the reset pulse.

Method and apparatus for generating a reset pulse responsive to a

A method and system are provided for detecting and measuring a phase difference, linearly over a range of 360.degree., between the output signals from a primary stratum clock module (100) and a standby stratum clock module (120) in a telecommunications system, calculating the amount of time needed to delay the standby clock signal (.o slashed.2) enough to cancel the phase difference, and controlling a digital delay line (132) to shift the phase of the standby clock signal (.o slashed.2) accordingly and thereby cancel the phase difference. Both the frequency and phase alignments of the two clocks are thus maintained. Therefore, when the system or user switches operations from the primary stratum clock module (100) to the standby stratum clock module (120), phase-related transients are not generated, which results in a significant increase in the overall performance and reliability of the system.

Method and system for aligning the phase of high speed clocks in

A refresh control system and method for refreshing DRAM memory in a data processing system, such as a communications system, are disclosed. A timer increments a refresh request counter each time that a desired refresh interval elapses. The contents of the refresh request counter is compared with the contents of a burst refresh counter, and a bus request signal generated responsive to the contents differing from one another, such difference indicating that a refresh operation should be performed. The bus arbitration scheme assigns no higher priority to the refresh priority request than for other bus operations; at such time as bus access is granted to the refresh operation, burst refresh is performed until the contents of the burst refresh counter again match the refresh request counter, at which time the bus is released. An emergency high priority bus request is generated when the difference between the contents of the refresh request counter and the burst counter exceed a given limit, indicating that violation of the refresh specification is imminent.

Refresh control method and system including request and refresh counters

A message priority scheme for use in local areas networks (LANS) operating in accordance with carrier sense, multiple access/collision detect (CSMA/CD) bus access protocol. A LAN station having a high priority message to send ignores the carrier sense signal, and thereby obtains immediate bus access. If the high priority message collides with another message already on the bus, both messages are subject to a backoff period. However, the backoff period for a high priority message is guaranteed to be less than that of a low priority message for a certain number of re-transmission attempts. An intermediate priority status is assigned to a message that previously had a high priority status, after a certain number of transmission attempts. The intermediate priority message is deprived of its ability to transmit while ignoring the carrier sense signal, but retains its shorter backoff period.

Local area network with message priority

A circuit is shown for arbitrating between inputs to provide all request inputs with the opportunity to be polled in substantially less time than is the case with known prior art round robin arbiters. This is accomplished by phase delaying the input clock to produce a plurality of different phase clock signals such that multiple arbiter circuits can be polled within a single clock cycle if the first few arbiter circuits do not have a request waiting. With proper speed of operation of arbiter circuits, the phase delay can be of a short enough duration that all of the arbiter circuits can be polled in a single clock cycle. With slower speed arbiter circuits, the total polling time can exceed one clock cycle but still be less than the number of clock cycles of prior art round robin circuits which typically was the number of arbiter circuits times a single clock cycle time duration.

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Richardson, TX, United States of America

David W Kuddes