Synopsys, Inc.

David W Knapp

Ronald A Miller

Tai A Ly

Donald B MacMillen

Donald B Macmillen

A method and an apparatus for creating a representation of a circuit with a pipelined loop from an HDL source code description. It infers a circuit including a pipelined loop which has cycle level simulation behavior matching that of the source HDL. Loop carry dependencies and memory and signal I/O accesses within the loop are scheduled correctly.

Methods for automatically pipelining loops

A method and an apparatus for coupling the results of behavioral synthesis with those of logic synthesis. It uses a timing verifier to precalculate the timing characteristics of a circuit for use by behavioral synthesis. Timing for control chaining is included in the precalculated timing characteristics. Once behavioral synthesis is complete, logic synthesis is informed of timing constraints introduced by behavioral synthesis.

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Palo Alto, CA, United States of America

David W Knapp