Agere Systems Inc.

Cardiac Pacemakers, Inc.

Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Lucent Technologies Inc.

Boston Scientific Scimed, Inc.

University of Minnesota

Vtc Inc.

Polar Semiconductor, Inc.

David W Kelly

Ross Wilson

Jason P Brenden

Daniel James Dolan, Jr

Michael Joseph Peterson

Richard Rauschmayer

Gregory J Sherwood

Cameron Carroll Rabe

Justin Theodore Nelson

Jeffrey A Gleason

Stephen Carl Kuehne

Robert Alan Norman

Suneel Arora

Keith R Maile

William J Linder

Daniel Charles Kerr

Travis Roger Oenning

Alan Sangone Chen

Peter John Windler

Angelo Rocco Mastrocola

Robert D Dreher

Jason S Goldberg

Scott M O'Brien

Anamul Hoque

Robert Wimmer

Paul Mazur

Jaydip Bhaumik

David Fitzgerald

Suharli Tedja

Michael W Dooley

James Patrick Howley

Jean-Cheui Hsung

Daniel J Dolan, Jr

Michael John O'Brien

Joseph D Stenger

William A Palm

Ronen Malka

Richard J Wessels

Jason A Christianson

Lloyd A Van Hofwegen

Haoyan Chen

Ram S Narayan

Carol G Stadler

Jeffrey Laackmann

Nathan M Rudd

William D Jensen

Adam Lipsey

Embodiments herein relate to systems and devices for measuring analyte presence on graphene varactors, which can be used for analyte sensing in physiological gas samples. In an embodiment, a system for measuring analyte presence on a graphene varactor is included having a capacitance to digital converter (CDC) and a graphene varactor. The CDC can be in electrical communication with the graphene varactor and can be configured to measure the capacitance of the graphene varactor in response to an excitation signal over a plurality of DC bias voltages. Other embodiments are also included herein.

Systems and methods for analyte sensing in physiological gas samples

A method is provided, for example, to implement multiplexed communication between a controller and a preamplifier in a storage device. For example, multiplexed communication is implemented by controlling a bidirectional serial data line of a digital bus to selectively transmit digital signals in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller, in response to a direction control signal, and concurrently transmitting a synchronous clock signal over a clock signal line of the digital bus from the controller to the preamplifier to synchronize transfer and processing of the digital signals transmitted on the bidirectional serial data line of the digital bus. The direction control signal is transmitted from the controller to the preamplifier on one of the bidirectional serial data line and the clock signal line of the digital bus.

Multiplexed synchronous serial port communication with skew control for storage device

Systems and method relating generally to data processing, and more particularly to systems and methods for utilizing multiple data streams for data recovery from a storage device.

Systems and methods for multi-path preamplifier fault processing

A method is provided to enable communication between a controller and a preamplifier in a storage device. For example, the method includes implementing a serial port which is configured to transmit digital signals between the controller and the preamplifier over a single bidirectional serial data line. The serial port is controlled to selectively transmit digital signals over the bidirectional serial data line in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller.

Serial port communication for storage device using single bidirectional serial data line

A method is provided, for example, to implement multiplexed communication on an analog bus between a recording channel and a preamplifier in a storage device. A first input of read data circuitry within the recording channel is switchably connected to a first analog line of the analog bus to receive read data transmitted from the preamplifier to the recording channel over the first analog line during a read operation. In addition, a write data output of write data circuitry within the recording channel is switchably connected to the first analog line of the analog bus to transmit write data from the recording channel to the preamplifier over the first analog line during a write operation.

Multiplexed communication in a storage device

An apparatus for measuring cross-talk in an array reader magnetic storage system includes an array reader with multiple read heads operable to read data from a magnetic storage medium, a first preamplifier connected to a first read head, a second preamplifier connected to a second read head, and a cross-talk measurement circuit connected to the first preamplifier and to the second preamplifier, operable to measure cross-talk between a first signal from the first read head and a second signal from the second read head.

Cross-talk measurement in array reader magnetic recording system

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for synchronizing operations in a data storage system.

Systems and methods for timing control in a data processing system

A storage system with pattern dependent write includes a magnetic write head, a magnetic storage medium, a read channel operable to process write data to be recorded on the magnetic storage medium by the magnetic write head, and a preamplifier operable to receive the write data and an associated clock from the read channel, to generate a pattern dependent write control signal based on a pattern in the write data and on the clock, and to set a write current level through the magnetic write head to a number of different current levels based on the pattern dependent write control signal.

Storage system with pattern dependent write

Various systems and methods for reducing cross coupling in proximate signals are disclosed. As one example, a system for reducing cross-coupling in adjacent signals that includes an active slew rate limiter circuit is disclosed. The active slew rate limiter circuit is operable to receive an input signal, and to provide an output signal based on the input signal with a controlled slew rate. In some cases, such systems may be included within a storage device that includes a read head. In such cases, the systems may operate to assure a substantially constant power dissipation within the read head.

Systems and methods for reduction of cross coupling in proximate signal lines

A level-shift circuit translates a control signal to a level-shifted output. The level-shift circuit includes a pulse generator circuit for providing Set and Reset pulses based on the control signal and a level-shift circuit for translating the Set and Reset pulses to level-shifted Set and Reset pulses. First and second differential detectors are connected to monitor the level-shifted Set and Reset pulses to provide detection of communicated Set and Reset pulses despite the presence of transients in the level-shift circuit. A gate drive circuit employs the Set and Reset pulses communicated by the differential detectors to generate a gate drive signal.

Differential high voltage level shifter

A voltage regulator, a method of regulating voltage and an IC including a voltage regulator. In one embodiment, the voltage regulator includes: (1) a DC precision amplifier configured to generate a DC precision signal based on a reference voltage and a regulated output of the voltage regulator and (2) a response amplifier, coupled in parallel with the DC precision amplifier, configured to generate an error signal based on the reference voltage and the regulated output, the response amplifier further configured to generate the regulated output based on a regulating signal comprised of the error signal and the DC precision signal. The DC precision amplifier may be a CMOS amplifier and the response amplifier may be a NPN amplifier.

Output compensated voltage regulator, an IC including the same and a method of providing a regulated voltage

Electronic circuitry and methods are disclosed for monitoring a portion of a write driver, for example, a steady state value of a write driver of a hard disk drive preamplifier. Based on a result of the monitoring, a condition, such as a fault, can be detected in the write driver. For example, apparatus for monitoring a write driver of a disk drive system comprises a comparator circuit coupled to an output of the write driver and configured to compare a value present at the output of the write driver with a reference value such that at least one condition associated with the write driver is detectable as a result of the comparison of the write driver output value and the reference value.

Write driver monitoring and detection

An apparatus and method for controlling the common mode voltage across a data storage device write head. The write current is supplied by a first plurality of parallel current sources each independently activated to limit the common mode voltage generated across the write head. A plurality of parallel resistive elements responsive to current supplied by a second plurality of parallel current sources bias an output transistor that further controls the write current. Each of the plurality of parallel resistive elements and each of the second plurality of parallel current sources is also independently activated to limiting the common mode voltage generated across the write head.

Apparatus and method for controlling common mode voltage of a disk drive write head

An integrated circuit having an n-channel MOSFET device and a JFET device. The integrated circuit includes a semiconductor layer having an upper surface, an MOS transistor device formed in a doped well of a first conductivity type extending from the semiconductor upper surface and a JFET device. The JFET device includes a channel region in the semiconductor layer spaced from, and having a peak concentration positioned a predetermined distance below, the upper surface. An associated method of manufacturing includes introducing p-type dopant into the semiconductor surface to form a p-well in which the NMOS device is formed and a source and a drain of the JFET device. N-type dopant is introduced into the semiconductor surface to form an n-type region of the NMOS device below the p-well and a gate region of the JFET device. P-type dopant is introduced into the semiconductor layer to simultaneously form a higher concentration p-type region in the p-well of the NMOS device and a channel region extending between the source and drain of the JFET.

Integrated circuit with depletion mode JFET

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Eagan, MN, United States of America

David W Kelly