Hewlett-packard Development Company, L.p.

Digital Equipment Corporation

Other

Hewlett-packard Company

Sun Microsystems, Inc.

Compaq Computer Corporation, Inc.

Oracle America, Inc.

David W Hartwell

Elbert Bloom

Samuel Hammond Duncan

Victoria M Triolo

Richard Eugene Kessler

David Martin Fenwick

Denis J Foley

Ricky C Hetherington

Stephen R Van Doren

Brett C Ong

Darrel D Donaldson

Hansel A Collins

Steve Lang

David T Mayo

David Golden

David A J Webb, Jr

Maurice B Steinman

Timothy W Olesiewicz

Charles Patrick Thacker

John K Grooms

Steven Ho

Mark Hong Chen

Lawrence A Chisvin

Stephen Lindquist

Scott E Breach

Dale R Keck

Andrej Kocev

Joseph F Rantala

Darrell D Donaldson

Rajen S Ramchandani

Glenn A Herdeg

Frederick C Canter

Jeffrey Willcox

Roger Pannel

Arvind Kumar

John Eble

A mezzanine board alignment and mounting device includes a multi-stage pin connected to a main board near a mezzanine board connector disposed on the main board. The multistage pin includes a base adapted to connect to the main board, a point distal to the base adapted to pass through an opening on a mezzanine board, and a support disposed between the base and the point. A diameter of the point widens towards the support. A diameter of the support is wider than a diameter of the opening. When the point is fully inserted through the opening in the mezzanine board, the mezzanine board is aligned properly to connect with the mezzanine board connector on the main board.

Multi-function mezzanine board alignment and mounting device, with integrated handle

A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or more I/O devices are coupled to the I/O bridge ASIC, each I/O device capable of accessing machine resources in the computer system by transmitting and receiving message packets. Machine resources in the computer system include data blocks, registers and interrupt queues. Each processor in the computer system is coupled to a memory module capable of storing data blocks shared between the processors. Coherence of the shared data blocks in this shared memory system is maintained using a directory based coherence protocol. Coherence of data blocks transferred during I/O device read and write accesses is maintained using the same coherence protocol as for the memory system. Data blocks transferred during an I/O device read or write access may be buffered in a cache by the I/O bridge ASIC only if the I/O bridge ASIC has exclusive copies of the data blocks. The I/O bridge ASIC includes a DMA device that supports both in-order and out-of-order DMA read and write streams of data blocks. An in-order stream of reads of data blocks performed by the DMA device always results in the DMA device receiving coherent data blocks that do not have to be written back to the memory module.

Scalable efficient I/O port protocol

An expansion card bracket for a computer server has an expansion card support attachable to a motherboard and an expansion card accepting portion disposed near a top of the support. The expansion card accepting portion is configured to support an expansion card at an acute angle of inclination with respect to the motherboard. The acute angle of inclination is substantially equal to an angle of inclination of a connector for receiving the expansion card.

25 degree tool-less expansion card bracket

A computer system comprising a memory system that comprises a plurality of memory modules; and a memory controller that accesses the plurality of memory modules to service memory requests. The computer system also comprises an error-type memory controller that configures the noted access such that the memory controller can continue to access a failed one of the plurality of memory modules that incurred a soft error.

Restoring access to a failed data storage device in a redundant memory system

A system is disclosed that detects data forwarding clock errors including both missing and additional clock signals. The system provides for a phase locked loop (PLL) that locks onto a data forwarding source synchronous clock signal wherein the PLL outputs a system clock whose frequency is the average of the data forwarding clock frequency. The data forwarding clock signals and the system clock signals are counted separately and when a discrepancy occurs the receiving system is informed that an error has occurred. The receiving system will handle the error in its routine fashion. The counters and the PLL are synchronized to be sure that the PLL has acquired a lock before the error detection is enabled.

Detection of added or missing forwarding data clock signals

A phase and edge aligned local clock signal is generated in a data-receiving unit by deriving the local clock signal from a forwarded clock signal received from a transmitting unit. The local clock signal is a delayed replica of the forwarded clock signal, such that the receiving unit maintains synchronism between the local clock signal and the forwarded clock signal. Thus, transfers from an input latch to other components in the receiving unit can be effected in step with the receipt of data in the input latch.

Enhanced clock forwarding data recovery

A system and method for initializing and resetting a clocking subsystem having a phased locked loop (PLL) within an input/output interface of a data processing system. A first timer generates signals in response to receiving clock signals from a clock source. A second timer detects the presence or absence of signals from the first timer and in response to an absence outputs a circuit reset signal to a circuit. The circuit in turn issues a reset signal to the PLL and to other systems.

Clock forward initialization and reset signaling technique

An anti-starvation interrupt protocol for use in avoiding livelock in a multiprocessor computer system is provided. At least one processor is configured to include first and second control status registers (CSRs). The first CSR buffers information, such as interrupts, received by the processor, while the second CSR keeps track of the priority level of the interrupts. When an interrupt controller receives an interrupt, it issues a write transaction to the first CSR at the processor. If the first CSR has room to accept the write transaction, the processor returns an acknowledgement, whereas if the first CSR is already full, the processor returns a no acknowledgment. In response to a no acknowledgment, the interrupt controller increments an interrupt starvation counter, and checks to see whether the counter exceeds a threshold. If not, the interrupt controller waits a preset time and reposts the write transaction. If it does, the interrupt controller issues a write transaction having a higher priority to the second CSR. In response, the processor copies all of the pending interrupts from the first CSR into the memory subsystem, thereby freeing up the first CSR to accept additional write transactions.

Anti-starvation interrupt protocol

A system and method are provided for moving information between cache coherent memory systems of a partitioned multiprocessor computer system while containing faults to a single partition. The multiprocessor computer system includes a plurality of processors, memory subsystems and input/output (I/O) subsystems that can be divided into a plurality of partitions. Each I/O subsystem includes at least one I/O bridge for interfacing between one or more I/O devices and the multiprocessor system. The I/O bridge has a data mover configured to retrieve information from a &ldquo;source&rdquo; partition and to store that information within its own &ldquo;destination&rdquo; partition. When activated, the data mover issues a request to the source partition for a non-coherent copy of the information. The home memory subsystem in the source partition preferably responds to the request by sending the data mover &ldquo;valid&rdquo;, but non-coherent copy of the information, e.g., a &ldquo;snapshot&rdquo; of the information as of the time of the request. Upon receiving the information, the data mover may copy it into the memory subsystem of the destination partition.

Block data mover adapted to contain faults in a partitioned multiprocessor system

A phase-locked loop (PLL) circuit is used to synchronize data transfers between a fast clock and a slow clock domain. The data transfer can be deterministic, where the fast clocks are generated by a first PLL and the slow clocks are generated by a second PLL. The second PLL is used to create a phase relationship between the first PLL output clock and a third PLL output clock. The phase relationship can provide for a deterministic data transfer.

Deterministic hardware behavior between multiple asynchronous clock domains through the novel use of a PLL

A method and apparatus for accommodating the speed requirements of a DMA read request from PCI protocol I/O devices attached via a DMA to a multiprocessor system mesh. A bridge between the device controller and the mesh is described which buffers the data from the memory in cache lines from which the data is delivered finally to the I/O device. The system is adaptive in that the number of cache lines required in past reads are remembered and used to determine if the number of cache lines is reduced or increased.

Adaptive data fetch prediction algorithm

A system comprising a communications link between processors configured to transmit packets between transmitting and receiving processors. The communications link comprises a conduction path for each bit in the packet and the paths are grouped into separate bundles and routed along different paths. A forwarded clock signal is sent with each bundle. The processors operate with a clock frequency that is roughly three times as fast as the clock frequency of the forwarded clock signal. Data is transmitted on both rising and falling edges of the clock. The receiving processor comprises a recovery circuit to which it pulls the asynchronous data into the processor clock domain. The recovery circuit comprises a delay locked loop circuit configured to create a delayed copy of the clock signal with clock edges that are aligned with the center of the data window for the transmitted data.

System for recovering data in a multiprocessor system comprising a conduction path for each bit between processors where the paths are grouped into separate bundles and routed along different paths

An automated backplane cable connection system (and method) for manually connecting a cluster of processor modules to other modules or I/O boxes uses a programmed server management control console which identifies connection terminals provided on the processors/I/O boxes and controls LEDs which are associated with the connection terminals, on a one to one basis. The programmed server management console uses diagnostic circuitry and causes LEDs corresponding to connection terminals engaged by a newly made cable connection to initially light up, and enables them to turn off if the newly made cable connection is proper as verified by the diagnostic circuitry. The cluster of processor modules may be connected to a plurality of I/O boxes through an Ethernet LAN. The processor modules or I/O boxes may have sufficient nonvolatile memory to remember backplane cable connections which have already been made according to user needs, as initially guided by the programmed server management control console. From the memory, replacement of cables when necessary, is facilitated, without the need for assistance by the server management console. If connection changes are needed because of design modifications or additions, the server management control console would again be needed. If a newly made backplane connection is improper or is broken, the diagnostic circuitry will enable the corresponding LEDs to stay lit or to start flashing (depending in the design), thereby signaling need for intervention. Backplane cable connections may be made by semiskilled personnel by using this invention. Also, &ldquo;hot-add, hot-replace, hot-swap&rdquo; of connection is easily possible by this invention without interrupting continuity of operation of the system.

Automated backplane cable connection identification system and method

An initialization/reset circuit automatically resets and initializes a clocking subsystem having a phase locked loop (PLL) within a data processing system. The logic circuit is contained within an input/output (I/O) interface of the system. Clock signals are provided from a clock source of the data processing system to the PLL. In addition to the PLL, the initialization/reset logic circuit comprises a counter, a first timer circuit and a second watchdog timer.

System and method to automatically reset and initialize a clocking subsystem with reset signaling technique

Growing community of inventors

Bolton, MA, United States of America

David W Hartwell