Qualcomm Incorporated

David W Hansquine

Roberto Averbuj

Edward George Tiedemann, Jr

Avneesh Agrawal

Brian K Butler

Gwain Bayley

Paul E Bender

Richard Gerard Hofmann

Robert P Gilmore

Brett Christopher Walker

Wenqing Wu

Kendrick H Yuen

Richard Alan Moore

Jeff A Levin

Muhammad Asim Muneer

Clock signals are distributed on a chip by applying an oscillating magnetic field to the chip. Local clock generation circuits including magnetic field sensors are distributed around the chip and are coupled to local clocked circuitry on the chip. The magnetic field sensors may include clock magnetic tunnel junctions (MTJs) in which a magnetic orientation of the free layer is free to rotate in the free layer plane in response to the applied magnetic field. The MTJ resistance alternates between a high resistance value and a low resistance value as the free layer magnetization rotates. Clock generation circuitry coupled to the clock MTJs senses voltage oscillations caused by the alternating resistance of the clock MTJs. The clock generation circuitry includes amplifiers, which convert the sensed voltage into local clock signals.

Clock distribution using MTJ sensing

Embodiments disclosed herein address the need for a single wire bus interface. In one aspect, a device communicates with a second device via a single wire bus using a driver for driving the bus with a write frame comprising a start symbol, a write indicator symbol, an address, and data symbols. In another aspect, the device receives one or more data symbols on the single wire bus during a read frame. In yet another aspect, a device communicates with a second device via a single wire bus using a receiver for receiving a frame on the single wire bus comprising a start symbol, a write indicator symbol, an address, and one or more data symbols, and a driver for driving return read data associated with the address when the write indicator identifies a write frame. Various other aspects are also presented. These aspects provide for communication on a single wire bus, which allows for a reduction in pins, pads, or inter-block connections between devices.

Single wire bus interface

Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes a database. The database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The database allows rapid voltage level decisions. In one embodiment, a voltage offset is added to a voltage level retrieved from the database corresponding to a target operating frequency of the functional circuit(s). In another embodiment, a voltage level is retrieved from the database corresponding to a target operating frequency for and a temperature level of the functional circuit(s). The AVS may partially or fully controllable by a software-based module that consults the database to make voltage level decisions.

Temperature compensating adaptive voltage scalers (AVSs), systems, and methods

Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocol is disclosed. In an embodiment, a system is disclosed and includes a centralized built-in self-test (BIST) controller configured to store an algorithm to test a plurality of memory modules. The BIST controller stores the algorithm as a set of generalized commands that conform to a command protocol. The BIST controller is configured to send the set of generalized commands to a sequencer.

Built-in self test (BIST) architecture having distributed interpretation and generalized command protocol

A built-in self-test (BIST) architecture having distributed algorithm interpretation is described. The architecture includes three tiers of abstraction: a centralized BIST controller, a set of sequencers, and a set of memory interfaces. The BIST controller stores a set of commands that generically define an algorithm for testing memory modules without regard to the physical characteristics or timing requirements of the memory modules. The sequencers interpret the commands in accordance with a command protocol and generate sequences of memory operations. The memory interfaces apply the memory operations to the memory module in accordance with physical characteristics of the memory module, e.g., by translating address and data signals based on the row-column arrangement of the memory modules to achieve bit patterns described by the commands. The command protocol allows powerful algorithms to be described in an extremely concise manner that may be applied to memory modules having diverse characteristics.

Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocol

A distributed, hierarchical built-in self-test (BIST) architecture for testing the operation of one or more memory modules is described. As described, the architecture includes three tiers of abstraction: a centralized BIST controller, a set of sequencers, and a set of memory interfaces coupled to memory modules. The BIST controller stores a set of commands that generically define an algorithm for testing the memory modules without regard to the physical characteristics or timing requirements of the memory modules. The sequencers receive the commands and generate sequences of memory operations in accordance with the timing requirements of the various memory modules. The memory interfaces apply the memory operations to the memory module in accordance with physical characteristics of the memory module, e.g., by translating address and data signals based on the row-column arrangement of the memory modules to achieve bit patterns described by the commands.

Tiered built-in self-test (BIST) architecture for testing distributed memory modules

The present invention discloses a method and apparatus for efficiently reading and storing state metrics in memory to enhance high-speed ACS Viterbi decoder implementations. The method includes applying an addressing scheme that determines the address locations of source state metrics during a process cycle. The source state metrics are then read from the address locations during the process cycle and applied to an add-compare-select butterfly operation of a Viterbi algorithm implementation to generate target state metrics. The method then stores each of the target state metrics into the address locations previously occupied by the source state metrics. The method further provides an addressing scheme that determines the address locations of the source state metrics based on a process cycle counter that is incremented and rotated in accordance with the process cycle. The method also provides an addressing scheme that employs a predetermined function to determine the address locations of the source state metrics.

Method and apparatus for efficiently reading and storing state metrics in memory for high-speed ACS viterbi decoder implementations

The certainties of transmitted bits at predetermined locations in time are determined a priori. This information is then used to set the states of a Viterbi decoder to different state metrics in accordance with the certainties of the transmitted bits. High certainty of a transmitted bit results in resetting the states corresponding to that bit to a high state metric. In contrast, low certainty of a transmitted bit results in resetting the states corresponding to that bit to a low state metric. Resetting the states to different state metrics improves the decoding performance and shortens the time required to converge the decoding trellis by eliminating improbable paths.

Decoding with partial state information on a convolutionally encoded channel

A resource allocator for allocating at least two different types of hardware resources for users within a communication system, wherein the system supports up to a first predetermined number of users of one particular type and a second predetermined number of users of a second particular type. The resource allocator provides a mapping of resources, either from fixed resources to shared resources or from shared resources to fixed resources, which is both cost effective and transparent to software.

Resource allocator

A spreader architecture for direct sequence spread spectrum communications is disclosed. This single architecture can perform OOK, BPSK, or QPSK spreading modulation of a carrier. In the QPSK and BPSK modes, input data is spread by pseudonoise signals to produce digital representations of phase-modulated baseband in-phase and quadrature components. In the OOK mode, the spectrum of the baseband components is selectively spread according to the input data. In an exemplary application, the various modulation modes are used to encode the control and traffic channels of a code-division multiple-access cellular telephone system.

Spreader architecture for direct sequence spread spectrum communications

The present invention discloses a system and system of performing an add-compare-select butterfly operation in an implementation of the Viterbi algorithm. The system includes a first memory element for storing a plurality of source state metrics. The first memory element is coupled to a multiplexer which is capable of selecting between a first and second operating path based on even and odd clock cycles. The multiplexer is coupled to an add-compare-select mechanism, which calculates the target state metrics for each of the source state metrics. A second storage element, coupled to the add-compare-select mechanism and the multiplexer, is used to temporarily store the target state metrics while a third storage element stores a predetermined logic bit which corresponds to the lowest value target state metric. The multiplexer therefore selects the first operating path during even clock cycles and supplies the source state metrics from the first memory element to the add-compare-select mechanism to generate target state metrics. During odd clock cycles, the multiplexer selects the second operating path to access the second memory element and use the previously calculated target state metrics as intermediate source state metrics, such that the add-compare-select mechanism generates the target state metrics based on the intermediate source state metrics.

High-speed ACS for Viterbi decoder implementations

A voice and data communication system and method for receiving symbols for a plurality of channels into chunks included within buffers, each chunk holding symbols for only a corresponding one of the plurality of channels. As complete frames are received and decoded, the chunks holding the symbols, that are decoded, are freed up to be used for reception of newly arriving symbols included in newly arriving frames.

System and method for reducing deinterleaver memory requirements through chunk allocation

A serial Viterbi decoder having a chainback cache is provided for use in a mobile telephone. In one embodiment described herein, the decoder includes a branch error metric block, an add-compare-select unit, and a chainback block including a chainback RAM, a full chainback cache and chainback controller circuitry. The chainback cache caches decision bits from previous process cycles such that full chainback operations need not always be performed. The chainback cache is configured to cache on all reads. With the chainback cache, significant savings in power consumption and processing time may be achieved with only a relatively modest increase in the amount of circuitry required. In another embodiment, a full chainback cache is not provided. Rather, the chainback block instead includes an L&plus;1 bit RAM, an updown counter and a shift register configured to emulate a chainback cache. In still another embodiment, an L bit shift register is employed instead of the combination of the L&plus;1 bit RAM and updown counter. In the various embodiments, the chainback block may be configured to perform only one chainback read in each process cycle or may be configured to perform m chainback reads in each process cycle. In still other embodiments, the chainback block is configured to perform chainback operations based on a through b reads where the cache is accessed for each read after a reads have been done until b reads have been performed or a match is obtained. In still further embodiments, the chainback block is configured to perform chainback operations over multiple process cycles rather than only a single process cycle.

Cached chainback RAM for serial viterbi decoder

The certainties of transmitted bits at predetermined locations in time are determine a priori. This information is then used to set the states of a Viterbi decoder to different state metrics in accordance with the certainties of the transmitted bits. High certainty of a transmitted bit results in resetting the states corresponding to that bit to a high state metric. In contrast, low certainty of a transmitted bit results in resetting the states corresponding to that bit to a low state metric. Resetting the states to different state metrics improves the decoding performance and shortens the time required to converge the decoding trellis by eliminating improbable paths.

Growing community of inventors

Raleigh, NC, United States of America

David W Hansquine