Tensilica, Inc.

Calos Fund Limited Liability Company

Cadence Design Systems, Inc.

Apple Inc.

David W Goodwin

Dror E Maydan

Peter Mattson

Earl A Killian

Walter David Lichtenstein

Ricardo E Gonzalez

Albert Ren-Rui Wang

Pavlos Konas

Christopher Mark Songer

Darin Stamenov Petkov

Rangarajan Srinivasan

Akilesh Parameswar

Richard Ruddell

Nupur Bhattacharyya

Marines Puig Medina

Christopher Rowen

Peng Tu

Ding-Kai Chen

Steven Weng-Kiang Tjiang

Scott James Forstall

Gregory B Novick

Cahya Adiansyah Masputra

Joseph Sokol, Jr

Neil Gareth Crane

Matthew G Watson

Lucia Elena Ballard

Christopher Marcellino

Charles Srisuwananukorn

Darin Stemenov Petkov

A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Automated processor generation system and method for designing a configurable processor

Services for a personal electronic device are provided through which a form of background processing or multitasking is supported. The disclosed services permit user applications to take advantage of background processing without significant negative consequences to a user's experience of the foreground process or the personal electronic device's power resources. To effect the disclosed multitasking, one or more of a number of operational restrictions may be enforced. By way of example, thread priority levels may be overlapped between the foreground and background states. In addition, system resource availability may be restricted based on whether a process is receiving user input. In some instances, an application may be suspended rather than being placed into the background state. Implementation of the disclosed services may be substantially transparent to the executing user applications and, in some cases, may be performed without the user application's explicit cooperation.

Opportunistic multitasking

Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers. Thus, a description of the behaviors of the various standard and/or extension operations that compose the ISA of an instance of a standard or configurable processor is used to automatically generate a set of shared processor datapaths that implement the behavior of those operations.

Method and system for automatic generation of processor datapaths

Disclosed herein are techniques to execute tasks with a computing device. A first task is initiated to perform an operation of the first task. A buffer construct that represents a region of memory accessible to the operation of the first task is created. A second task is initiated to perform of an operation of the second task that is configured to be timed to initiate in response to the buffer construct being communicated to the second task from the first task.

Systems and methods for using a shared buffer construct in performance of concurrent data-driven tasks

Disclosed herein are techniques to manage access to a memory using a buffer construct that includes state information associated with a region of the memory. The disclosed techniques facilitate access to the region of memory through a direct memory access operation while the state information of the buffer construct is in a first state. The state information can be transitioned to a second state in response to a first instruction. The disclosed techniques also facilitate access to the region of memory through a cache operation while the state information of the buffer construct is in the second state is disclosed. The state information can be transitioned to the first state in response to a second instruction.

Systems and methods for managing memory using multi-state buffer representations

Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers. Thus, a description of the behaviors of the various standard and/or extension operations that compose the ISA of an instance of a standard or configurable processor is used to automatically generate a set of shared processor datapaths that implement the behavior of those operations. In addition, certain aspects may take one or more operations as well as one or more input semantics and either re-implement the input semantics automatically, or combine the input semantics with each other or with one or more other operations to automatically generate a new set of shared processor datapaths.

A concurrent and asynchronous system may be managed by monitoring the performance of a plurality of operations that access a designated region of memory. In that region of memory, an occurrence of a potentially non-deterministic event can be detected when at least one of the operations is a write operation. The occurrence of the potentially non-deterministic event may then be recorded.

System and method for detection of non-deterministic memory access events

In an embodiment, buffer constructs may be generated to be associated with any one of multiple mutually exclusive states, including an open state and a closed state. When the buffer construct is in the closed state, the region of memory represented by the buffer construct is made accessible to one or more direct memory access (DMA) operations. Upon completion of the one or more DMA operations, the buffer construct transitions from the closed state to the open state. The region of memory represented by the buffer construct is made accessible for use with one or more cache operations when the buffer construct is in the open state, so that the one or more cache operations are not in conflict with the one or more DMA operations.

System and method for managing memory using multi-state buffer representations

A computer system is provided that utilizes a buffer construct to manage memory access operations to a region of memory. The buffer construct may correspond to a data item or structure that represents a region of memory. Each task may control the buffer construct exclusively of other tasks, so that the region of memory that is represented by the buffer construct is only available to the controlling task. Another task that requires access to the region of memory must wait until the controlling task makes the buffer construct available. The controlling task makes the buffer construct available only when DMA or other memory access operations that are in progress become complete. In this way, the buffer construct acts as a token that synchronizes each of the concurrent tasks execution and ensures mutually exclusive access to the common region of memory.

System and method for using a shared buffer construct in performance of concurrent data-driven tasks

A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.

Automatic instruction set architecture generation

The present invention is directed to a system and method for adding programmer visible features to a microprocessor by using partially-explicit ISA constructs. The system includes a language for expressing the partially-explicit ISA constructs that describe VLIW instruction formats, slots, and operations. These partially-explicit instruction set constructs are used in conjunction with prior art instruction set constructs to describe a complete instruction set. The system also includes a method for converting a partially-explicit instruction set to an explicit instruction set, which can then be used as described in prior art processor generation systems to generate fully-pipelined micro-architectural implementations in the form of synthesizable HDL, and to generate software components for extending software development tools for the microprocessor. Because the partially-explicit instruction set constructs are easier to write, modify, and maintain than prior art instruction set constructs, the invention significantly simplifies the process of describing an instruction set.

System and method for automatic conversion of a partially-explicit instruction set to an explicit instruction set

Method and system for automatic generation of processor datapaths using instruction set architecture implementing means

Growing community of inventors

Los Altos, CA, United States of America

David W Goodwin