Flir Systems, Incorporated

Photon Dynamics, Inc.

Q-Dot, Inc.

Flir Advanced Imaging Systems, Inc.

David W Gardner

Andrew M Hawryluk

Thomas E Linnenbrink

Henry Allen Hill

Brian P Higgins

Stephen D Gaalema

Rebecca S Reed

Kerry D Rhea

Peter C Roberts

In one embodiment, a camera is provided that includes: an image sensor configured to provide an image signal; an automatic gain control (AGC) unit configured to determine an AGC control signal for controlling a gain applied to the image signal; a cooler configured to cool the image sensor; and a thermal control circuit configured to compare the AGC control signal to a threshold, wherein the thermal control circuit is further configured to turn on the cooler if the comparison indicates that the AGC control signal exceeds the threshold.

Intelligent power management for actively-cooled cameras

An alignment metrology and resolution measurement system concurrently determines the alignment of an imaging array in six degrees of freedom relative to an external reference frame, and further determines the resolution of the imaging array. To achieve this, an image of at least three mask patterns is projected on the imaging array. First and second positions of the imaging array relative to first and second coordinate axis of the reference frame is obtained using pixel positions of the images along the first and second axis. A first rotational position of the imaging array about a third coordinate axis is obtained using pixel positions of the images along the first and second axes. The third position and the second and third rotational positions of the imaging array about the first and second coordinate axis are determined using feature widths of focus images of the patterns and distances between the mask patterns.

Alignment metrology and resolution measurement system for imaging arrays

Each sensor of a linear array of sensors includes, in part, a sensing electrode and an associated feedback circuit. The sensing electrodes are adapted to be brought in proximity to a flat panel having formed thereon a multitude of pixel electrodes in order to capacitively measure the voltage of the pixel electrodes. Each feedback circuit is adapted to actively drive its associated electrode via a feedback signal so as to maintain the voltage of its associated electrode at a substantially fixed bias. Each feedback circuit may include an amplifier having a first input terminal coupled to the sensing electrode and a second input terminal coupled to receive a biasing voltage. The output signal of the amplification circuit is used to generate the feedback signal that actively drives the sensing electrode. The biasing voltage may be the ground potential.

Method for capacitive testing of flat panel displays

The anti-blooming structure of an image sensor is supplied with varying voltages during different integration periods such that charges generated in response to low level light are fully captured, whereas charges generated in response to a bright light spill over in a controlled manner. Accordingly, sensor's response may be generated to result in higher gains at low light levels and progressively lower gains at the higher light levels.

Sensor-based gamma correction of a digital camera

Direct detect sensor for flat panel displays

An improved CCD imaging array is disclosed which is capable of operating at 10,000 frames-per-second. The imager consists of an array of 512.times.512 pixels having 16 serial output channels which provides a composite output data rate up to 250 Megasamples/second. The serial output registers are constructed from peristaltic CCDs, each having a GaAs FET output circuit bump-mounted to the silicon substrate. A four-layer pinned photodiode is utilized as the photodetector, and each photodiode has its own antiblooming drain. The antiblooming gates double as an optical shuttering device. Sample-and-hold output circuitry is also provided.

High-speed peristaltic CCD imager with GaAs fet output

The high speed data pathway system is used to convey data signals to integrated circuits connected to mother and daughter boards. The integrated circuits include a package and an integrated circuit chip carried by the package. An internal transmission line is carried by the package and coupled to the integrated circuit chip. The package includes both input and output connections for the internal transmission line. A high speed pathway is formed by serially connecting the internal transmission lines with external transmission lines to form a unified transmission medium. Advantageously, the internal transmission lines, external transmission lines and the connection between them have substantially corresponding characteristic impedances.

Growing community of inventors

Colorado Springs, CO, United States of America

David W Gardner