Motorola Corporation

Freescale Semiconductor,inc.

Semiconductor Components Industries, LLC

David W Feldbaumer

Mark B Weaver

Darren V Weninger

Rimon Shookhtim

Robert L Vyne

Cecil Aswell

Barry B Heim

Eric C Maass

Virgilio A Fernandez

Jan-Chung Wong

Vickie Mercier

Paul B Sofianos

Frederick L Lum

A dual-port voltage control oscillator for use in a frequency synthesizer has first and second input ports and an output. The first port is coupled in a phase-locked-loop configuration for receiving input data and a reference frequency. The phase-locked-loop tunes the oscillator in response to a channel selection and trim parameter. The second port of the oscillator has a variable gain characteristic. A multiplier is coupled to the second port for multiplying the input data by a transfer function to alter the input data thereby compensating for the second port variable gain characteristic.

Method and apparatus for compensating deviation variances in a 2-level FSK FM transmitter

An enable propagation controller employed in an integrated circuit operates in either a sequence manager mode or a transparent mode. When operating in the sequence manager mode, the enable propagation controller allows a set of signals intended to enable either a set of transmission or a set of reception signals to pass through to their corresponding transmission or receptions sub-circuits. Each of the signals in the desired set is allowed to pass through in a predetermined sequence and for a predetermined duration that may or may not be influenced by a set of control bits received by the enable propagation controller. When operating in a transparent mode, all enable signals are allowed to pass through to corresponding intended sub-circuits.

Enable propagation controller

A timing based adaptive equalization circuit ( ) dynamically monitors a signal received at an input terminal ( ) and compensates for attenuation losses in the transmission of the signal by adjusting an equalization value that increases or decreases the equalization of the signal. A digital phase locked loop control circuit ( ) centers the transition of the equalized signal in a delay line circuit ( ). An analog delay locked loop circuit ( ) provides a fixed throughput time for matching delay elements of delay line circuits ( and ) in the adaptive equalization circuit ( ). Timing signals propagating in the delay line circuits ( and ) are stored in sampler circuits ( and ). The equalization value for equalizing the input signal is adjusted based on stored logic values of specific storage elements in the sampler circuits ( and ).

Adaptive equalization circuit and method

A computer implemented method for generating an integrated circuit design (11) is provided. A description of a circuit (16) is provided in a format such as a Hardware Description Language (12). A functional simulation (17) of the description is run to determine functionality of the circuit. A netlist conversion (18) converts the description to a netlist comprising both a single-ended and differential circuit. The netlist conversion (18) converts the description to a single-ended description (24), replaces single-ended cells with differential cells and interconnects the differential cells (25), and exchanges terminals of the differential cells to maintain logic equivalence (26). A simulation with timing (19) is run on the netlist to verify timing characteristics of the circuit. The netlist is then provided to a router to generate a physical circuit layout (20) having both single-ended and differential circuits.

Computer implemented method for generating an integrated circuit design

A method for predicting yields for integrated circuit designs for given specification limits and process variations with respect to transistor parametric variations is based on a stastical analysis starting with response surface modeling techniques that relate desired circuit outcomes as a function of a set of defined independent variables. The response surfaces are converted to discrete C.sub.pk surfaces for all combinations of the independent variables. The C.sub.pk surfaces are next converted to discrete percent yield surfaces for each of the circuit outcomes which then are combined to provide a composite yield surface comprising all desired parametric operating points of the outcomes that may be used to predict the circuit yield.

Yield surface modeling methodology

A bus termination circuit actively switches a terminating resistor from the bus conductor in response to a control signal. A first state of the control signal connects the bus conductor through the terminating resistor to a voltage reference source, while a second state of the control signal isolates the bus conductor from the voltage reference source. Thus, the switchable active bus termination circuit can be permanently installed in computer peripheral devices and activated by the control signal.

Switchable active bus termination circuit

An active integrated termination circuit for providing a predetermined impedance at an output includes first and second resistors each having one end of which is commonly connected to the output. A first switching element is coupled between the other end of the first resistor and a first power supply conductor and is responsive to control signals for selectively coupling and de-coupling the first resistor to the first power supply conductor. A second switching element is coupled between the other end of the second resistor and a second power supply conductor and is responsive to the control signals for selectively coupling and de-coupling the second resistor to the second power supply conductor. The first and second resistors are polycrystalline silicon resistors and are trimmed to predetermined values by pulsing a high current unilaterally therethrough.

Precision switchable bus terminator circuit

A CMOS multiplexing circuit is provided for selecting one of a plurality of input signals under control of a digital select signal for providing an output signal inverted with respect to the selected input signal. A plurality of processing channels one for each input signal and each having exactly first, second, third and fourth transistors serially connected between first and second sources of operating potential are repsonsive to the digital select signal whereby only the second and third transistors in the selected processing channels are enabled. The other processing channels supporting the remaining input signals are disabled. The first and fourth transistors of the selected processing channel are alternately enabled by one of the plurality of input signals for providing the inverse state thereof at the output formed at the interconnection of the second and third transistors. The first and second sources of operating potential need pass through only two transistors which improves the propagation delay and since only the second and third transistors of the selected processing channels are conducting, the transistors forming the remaining non-selected processing channels are effectively removed from the output terminal thereby reducing the capacitive load thereon and improving the propagation delay in the select path.

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Chandler, AZ, United States of America

David W Feldbaumer