Ltx Corporation

Other

David W Curry

Phillip D Burlison

Mark E Deome

Tommie Edward Berry

Christopher Joel Hannaford

Eric H Rosenfeld

David Menis

Roger W Blethen

H Neil Kelly

Jeffrey H Perkins

Edward J Terrenzi

Kenneth J Lanier

Michael Carlyle Davis

Donald Vick Organ

William Robert Creek

Philip Earle Perkins

Michael Gordon Davis

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

Single platform electronic tester

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patters to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

A mixed signal integrated circuit testing system includes a system controller connected to a test head for controlling the testing operations of the mixed signal integrated circuit testing system. The test head is adapted to support a wide combination of both the analog and digital circuit testing modules. A DUT board, typically configured for a specific IC or family of ICs, is used to connect the circuit testing modules to the IC. The DUT board is connected to a DUT board interface that includes an analog DUT board interface adapter and a digital DUT board interface adapter. The digital DUT board interface adapter is connected directly to the digital circuit testing modules. The analog DUT board interface adapter is connected to a system configuration module that provides analog loading and conditioning circuitry as well as other circuitry that can be customized for testing specific ICs.

Mixed signal device under test board interface

The present invention is a putter head having a rear face, a ball striking face, a heel area, a toe area, an upper area and a lower area. An attaching device is secured to the upper area to enable a conventional shaft to be secured thereto. Extending through the rear face and between the heel area and toe area is a cavity. The upper area of the cavity is smaller in size than the lower area of the cavity. The putter includes a sole having six planes. The six planes are equally proportioned planes of the sole and will release one quarter of one inch from a centerline of the lower area. This will provide for an overspin being imparted on the ball soon after impact. This will innately result in a truer roll and less margin for error in the ball rolling on line to the hole.

Putter head

Growing community of inventors

Cohasset, MA, United States of America

David W Curry