International Business Machines Corporation

Other

Globalfoundries Inc.

David W Cummings

Michael Steven Siegel

Bartholomew Blaner

Jeff A Stuecheli

Guy L Guthrie

William John Starke

Jeffrey A Stuecheli

Jonathan R Jackson

Derek E Williams

Hugh Shen

Brian King Flachs

Aaron C Brown

George William Daly, Jr

James A McClurg

Nathan A Murati

Lakshminarayana Baba Arimilli

Bernard Charles Drerup

Brian Mitchell Bass

Phillip G Williams

Ronald Nick Kalla

Harmony Lynn Helterhoff

Michael C Mansell

Charles Marc Gobeil

Jeff Jerome Frankeny

Vasantha R Vuyyuru

Santosh Balasubramanian

Douglas A MacKay

Ambalath Matayambath Roopesh

Robert A Connell

Rachna Juneja Singhal

Embodiments of the present invention provide a system, method, and program product for accelerating a simulated memory walking sequence during a simulation conducted by a computer. In one embodiment, a simulation test-case is executed and one or more memory locations in the simulated memory are identified as eligible to contain valid data. Subsequent to commencement of the simulated memory walking sequence, it is determined whether an identified memory location is within a specified number of memory locations after a memory location to be processed by simulated hardware during the simulated memory walking sequence. If an identified memory location is within the specified number, the simulated hardware is allowed to process the memory location. If an identified memory location is not within the specified number, the simulated hardware is advanced to a subsequent memory location and is allowed to process the subsequent memory location.

Acceleration of memory walking sequences during simulation

A data structure includes a plurality of entries each corresponding to a different systemwide combined response of a data processing system. A particular entry includes identifiers of multiple possible actions that can be taken in response to a systemwide combined response. Master logic issues a memory access request on a system fabric of the data processing system. The master logic, responsive to receiving the systemwide combined response and a selection of one of the multiple possible actions from a source of the memory access request prior to receipt of the systemwide combined response, selects the particular entry based on the systemwide combined response and selects one of the multiple possible actions identified in the particular entry based on the received selection. The master logic services the memory access request in accordance with the systemwide combined response by performing the selected one of the multiple possible actions.

Selection of post-request action based on combined response and input from the request source

A method, system and computer-usable medium are disclosed for detecting the cause of a system hang in a verification environment. Hardware components associated with the design under test that are not included in the verification environment are replaced by software drivers. A dependency is set between a first driver and a second driver such that quiescing of the first driver is prevented until the second driver is quiesced. Each driver in a simulation test is designated to be either independent or dependent, with each dependent driver being associated with at least one independent driver. The independent driver is quiesced at a predetermined time. Dependent drivers do not quiesce until of their associated drivers have quiesced and completed all of their respectively issued instructions.

Generating and detecting hang scenarios in a partially populated simulation environment

A computer identifies a storage element in a simulation model of an integrated circuit design that, during simulation of the integrated circuit design using the simulation model, is subject to having its value forced. In response to identifying the storage element, an indication of the storage element and the associated clock signal are stored in a database. In response to receiving an input indicating the value of the storage element is to be forced during simulation, a determination is made by reference to the database whether or not forcing of the value is mistimed with reference to the associated clock signal. In response to a determination that the forcing of the value as indicated by the input is mistimed with reference to the associated clock signal, an indication that forcing of the value is mistimed is output.

Identification of mistimed forcing of values in design simulation

A coherent attached processor proxy (CAPP) within a primary coherent system participates in an operation on a system fabric of the primary coherent system on behalf of an attached processor (AP) that is external to the primary coherent system and that is coupled to the CAPP. The operation includes multiple components communicated with the CAPP including a request and at least one coherence message. The CAPP determines one or more of the components of the operation by reference to at least one programmable data structure within the CAPP that can be reprogrammed.

Programmable coherent proxy for attached processor

A coherent attached processor proxy (CAPP) of a primary coherent system receives a memory access request specifying a target address in the primary coherent system from an attached processor (AP) external to the primary coherent system. The CAPP includes a CAPP directory of contents of a cache memory in the AP that holds copies of memory blocks belonging to a coherent address space of the primary coherent system. In response to the memory access request, the CAPP performs a first determination of a coherence state for the target address and allocates a master machine to service the memory access request in accordance with the first determination. Thereafter, during allocation of the master machine, the CAPP updates the coherence state and performs a second determination of the coherence state. The master machine services the memory access request in accordance with the second determination.

Coherent attached processor proxy supporting coherence state update in presence of dispatched master

In the verification of an integrated circuit design having arbitration logic which controls access from a plurality of requesters to a shared resource, an arbitration stall simulation mechanism selects one or more of the requesters for an extended stall procedure, and when a global counter expires, applies stalls having controlled durations to the selected requesters. The controlled durations can be randomly generated time periods within a preset range. The number of requesters subjected to the extended stall procedure can be randomly selected based on a predetermined percentage of requesters to stall. Local (requester-specific) code can perform the stalls for respective requesters using a stall duration inputs. The requester-specific codes can carry out the stalls using application program interface calls to override respective arbiter inputs from the requesters.

Increasing coverage of delays through arbitration logic

The present invention is a method, system and framework for generating and processing XForms documents. Utilizing the method, system and framework of the present invention, developers need only write loosely coupled components that implement the minimal application-specific interface code, and the method, system and framework coordinates the generation and processing based on a description of the form's lifecycle. It also allows developers to reuse components created for other integrations that implemented the framework. The advantage of the method, system and framework is to significantly reduce development effort to integrate XForms with a vast number of applications, while all known solutions are specific to a single integration case.

Method and system for Xform generation and processing application integration framework

A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an external attached processor maintains, in each of a plurality of entries of a CAPP directory, information regarding a respective associated cache line of data from the primary coherent system cached by the attached processor. In response to initiation of recovery operations, the CAPP transmits, in a generally sequential order with respect to the CAPP directory, multiple memory access requests indicating an error for addresses indicated by the plurality of entries. In response to a snooped memory access request that targets a particular address hitting in the CAPP directory during the transmitting, the CAPP performs a coherence recovery operation for the particular address prior to a time indicated by the generally sequential order.

Accelerated recovery for snooped addresses in a coherent attached processor proxy

In response to receiving a memory access request and expected coherence state at an attached processor at a coherent attached processor proxy (CAPP), the CAPP determines that a conflicting request is being serviced. In response to determining that the CAPP is servicing a conflicting request and that the expected state matches, a master machine of the CAPP is allocated in a Parked state to service the memory access request after completion of service of the conflicting request. The Parked state prevents servicing by the CAPP of a further conflicting request snooped on the system fabric. In response to completion of service of the conflicting request, the master machine transitions out of the Parked state and issues on the system fabric a memory access request corresponding to that received from AP.

Coherent attached processor proxy supporting master parking

In response to receiving a memory access request and expected coherence state at an attached processor at a coherent attached processor proxy (CAPP), the CAPP determines that a conflicting request is being serviced. In response to determining that the CAPP is servicing a conflicting request and that the expected state matches, a master machine of the CAPP is allocated in a Parked state to service the memory access request after completion of service of the conflicting request. The Parked state prevents servicing by the CAPP of a further conflicting request snooped on the system fabric. In response to completion of service of the conflicting request, the master machine transitions out of the Parked state and issues on the system fabric a memory access request corresponding to that received from the AP.

In the verification of an electronic design such as a microprocessor, a set of generic transaction types is applied to a unit in a unit simulation environment and then the same set of generic transaction types is applied to the unit in a larger (e.g., element) simulation environment using an abstraction layer which can interface with both a unit translation layer of the unit simulation environment and an element translation layer of the element simulation environment. The abstraction layer may comprise a generic driver interface which issues generic commands having command parameters including a command type, an address, and operand data. The invention can be extended to multiple units which make up the element, or to multiple elements in the element environment. The invention can further be extended in a hierarchical fashion to other levels of simulation environments, e.g., unit-element-system.

Growing community of inventors

Round Rock, TX, United States of America

David W Cummings