Intel Corporation

David W Clift

Andrew F Glew

Robert P Colwell

James M Arnold

Glenn J Hinton

David J Sager

David B Papworth

Darrell D Boggs

A mechanism is provided for allowing a processor to recover from a failure of a predicted path of instructions (e.g., from a mispredicted branch or other event). The mechanism includes a plurality of physical registers, each physical register can store either architectural data or speculative data. The apparatus also includes a primary array to store a mapping from logical registers to physical registers, the primary array storing a speculative state of the processor. The apparatus also includes a buffer coupled to the primary array to store information identifying which physical registers store architectural data and which physical registers store speculative data. According to another embodiment, a history buffer is coupled to the secondary array and stores historical physical register to logical register mappings performed for each of a plurality of instructions part of a predicted path. The secondary array is movable to a particular speculative state based on the mappings stored in the history buffer, such as to a location where a path failure may occur. The secondary array can then be copied to the primary array when a failure is detected in a predicted path of instructions near where the secondary array is located to allow the processor to recover from the predicted path failure.

Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointer

A technique for enhancing performance for code transitions of floating point and packed data modes, in which a tag incorrect (TINC) bit is used to indicate a potential fault condition when transitioning between the modes. When tags of a floating point/packed data registers are not at the expected value for the mode transition, the TINC bit is used to a substitute condition which prevents the generation of the fault condition.

Performance enhancement for code transitions of floating point and packed data modes

A data processor includes a plurality of physical registers and a decoder that decodes a stream of instructions into micro-operations which include speculative operations specifying associated logical registers. The data processor further includes a register-alias table having a plurality of addressable entries corresponding to logical registers, specified by the speculative operations. Each entry of the register-alias table contains a register pointer to a corresponding physical register. The processor further includes a retirement register file that maintains register values of non-speculative operations, and a retirement array that maintains a retirement ordering for the retirement register file. Both the register-alias table and retirement array are updated by circuitry that is responsive to a register exchange operation; the circuitry swapping register pointers associated with first and second entries, respectively.

Data processor with circuitry for handling pointers associated with a

A Register Alias Table (RAT) for floating point and integer register renaming within a superscalar microprocessor. The RAT provides register renaming of integer and floating point registers and flags to take advantage of a larger physical register set than would ordinarily be available within a given macroarchitecture (such as the Intel architecture or Power PC or Alpha designs) and thereby eliminate false data dependencies that reduce overall superscalar processing performance. As uops are simultaneously presented to the RAT logic, their logical sources (both floating point and integer) are used as indices into a RAT array to look up the corresponding physical registers which reside within a Re-Order Buffer (ROB) where the data for these logical source is found. The ROB is composed of many multiple-bit physical registers. During the same clock cycle, the RAT array is updated with new physical destinations granted by an Allocator such that uops in future cycles can read them for their physical sources. Logic is provided for performing prioritized table reads in parallel for all uops and prioritized table writes in parallel for all ups. There is a separate integer and floating point RAT. Up to four uops may be processed by the RAT logic within a given clock cycle.

Integer and floating point register alias table within processor device

A Register Alias Table (RAT), including a retirement floating point RAT array, for floating point register renaming within a superscalar microprocessor capable of speculative execution. The RAT provides register renaming floating point registers to take advantage of a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs) and thereby eliminate false data dependencies that reduce overall superscalar processing performance. As a set of uops is presented to the floating point RAT logic, their logical sources are used as indices into a floating point RAT array to look up the corresponding physical registers which reside within a Re-Order Buffer (ROB) where the data for these logical sources is found. An efficient FXCH operation is implemented within the floating point RAT mechanism by switching 6-bit physical register pointers rather than switching the actual data for each physical register which is 86-bits wide. There is a retirement floating point RAT array with dual valid bits and a dual TOS pointer to account for speculative FXCH operations in addition to another floating point RAT array. The retirement floating point RAT array is updated only upon uop retirement whereas the floating point RAT array is updated at uop issuance.

Floating point register alias table FXCH and retirement floating point

A register alias table unit (RAT) with an idiom recognition mechanism for overriding partial width conditions stalls is described. A partial width stall condition occurs during the RAT renaming process when a logical source register being renamed is larger than the corresponding physical source register pointed to by a renaming table. An idiom recognizer detects uops that zero their logical destination register and sets and clears zero bits in an iRAT array accordingly. The zero bits indicate which portions of an entry's physical source register are known to be zeros. A partial width stall override mechanism overrides a partial width stall condition when the zero bits for the physical source register causing the partial width stall indicate that the 'missing' portion of the physical source register contains zeros. The performance of a microprocessor implementing such a RAT renaming mechanism with an idiom recognizer is improved because common partial width stalls are avoided.

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Hillsboro, OR, United States of America

David W Clift