Freescale Semiconductor,inc.

Motorola Corporation

Nxp Usa, Inc.

Intrinsity, Inc.

David W Chrudimsky

Padmaraj Sanjeevarao

Jon Scott Choy

Thomas Jew

William C Moyer

James S Blomgren

Michael R Seningen

Stephen C Horne

Bruce L Morton

Clinton C Kuo

Ronald J Syzdek

Xiaojie He

Timothy J Strauss

Tahmina Akhter

Edward Bryann C Fernandez

Richard Kazuki Eguchi

Transitioning to all addresses of a memory array during BIST includes arranging the addresses as a matrix with rows of the matrix corresponding one to one to the plurality of addresses of the memory array and columns of the matrix corresponding one to one to the plurality addresses of the memory array. A column of a selected current location can correspond to a destination address of a memory transition. The destination addresses can identify a candidate row of the matrix which corresponds to the destination address. The candidate row can be different from a row of the current location. A next location can be determined that has not been recorded in the candidate row that has a minimum column distance from the column of the first location as compared to other locations that have not been recorded in the candidate row.

Full address coverage during memory array built-in self test with minimum transitions

A memory system has a decoder circuit that includes a first driver circuit having an input coupled to receive a first pre-decode signal. The first driver circuit includes transistors wherein a first current electrode of a first transistor is coupled to receive a second pre-decode signal. The decoder circuit includes a second driver circuit having an input coupled to receive a third pre-decode signal. The second driver circuit includes transistors wherein a first current electrode of a third transistor in the stack is coupled to receive the second pre-decode signal. A fifth transistor has a first current electrode coupled to an output of the first driver circuit, a second current electrode coupled to an output of the second driver circuit, and a control electrode coupled to a fourth pre-decode signal.

Decoder

A latching level shifter coupled to a first power supply voltage is driven by a logic circuit coupled to a second power supply voltage. The latching level shifter is driven in a first mode to store a state based on an input signal received by the logic circuit, the first and second power supply voltages are set at first and second initial voltage levels. The latching level shifter is driven in a second mode subsequent to the first mode, the first power supply voltage is set to an intermediate voltage level. The latching level shifter is driven in a high voltage protection mode to produce an output voltage based on the state, the first power supply voltage is set to a final voltage level that is greater than a final voltage level of the second power supply voltage. The high voltage protection mode is subsequent to the second mode.

Latching level shifter and method of operation

A word line driver that includes a pull up transistor for biasing a node of a stack of transistors that are located between a high supply voltage terminal and a low supply voltage terminal. The node is biased at a voltage that is between the high supply voltage and the low supply voltage. The stack of transistors includes a stack of decode transistors and a cascode transistor. The cascode transistor is located between the node and a second node of the stack that is coupled to an inverting circuit.

Non-volatile memory (NVM) with word line driver/decoder using a charge pump voltage

A memory module decodes an address to determine a one or more wordline select pattern, or other spatial select pattern. An encoder determines an encoded value based upon the wordline select pattern that is compared to an expected encode value. The encode value has fewer than twice the number of address bits used to determine the wordline select pattern.

Memory device and method using encode values for access error condition detection

A method for accessing a memory includes receiving a first address wherein the first address corresponds to a demand fetch, receiving a second address wherein the second address corresponds to a speculative prefetch, providing first data from the memory in response to the demand fetch in which the first data is accessed asynchronous to a system clock, and providing second data from the memory in response to the speculative prefetch in which the second data is accessed synchronous to the system clock. The memory may include a plurality of pipeline stages in which providing the first data in response to the demand fetch is performed such that each pipeline stage is self-timed independent of the system clock and providing the second data in response to the speculative prefetch is performed such that each pipeline stage is timed based on the system clock to be synchronous with the system clock.

Multiple access type memory and method of operation

A first logic state is at a first output voltage level at a first output of a level shifter that selects a first negative regulation voltage level in response to the first logic state. A negative supply voltage begins at first potential and decreases to the first negative regulation voltage level. The first output voltage level decreases as the negative supply voltage decreases. The first output of the level shifter is switched from the first logic state to a second logic state in response to the negative supply voltage reaching the first negative regulation voltage level. The second logic state is provided at a second output voltage level that selects a second negative regulation voltage level for the negative regulation voltage. The first output of the level shifter remains at the second logic state but is reduced in voltage.

Negative voltage generation

A memory including a data line, a sense amplifier, and an array of memory cells. The memory includes a transistor for coupling the data line to memory cells of the array for reading. The transistor is biased at a voltage that is higher than a voltage that the data line is biased during precharging. The transistor is part of a regulation circuit. The regulation circuit includes transistors with a higher dielectric breakdown voltage than transistors of the sense amplifier.

Memory with high speed sensing

A memory has first and second memory arrays and first and second sense amplifiers coupled to the first and second memory arrays, respectively. A verify data line is coupled to first outputs of the first sense amplifier and the second sense amplifier as well as to a program/erase controller. The verify data line has a first logic circuit having a first input coupled to the first output of the first sense amplifier and an output. A second logic circuit has a first input coupled to the output of the first logic circuit, a second input coupled to the first output of the second sense amplifier, and an output. A global data line is coupled to a second output of the first sense amplifier and a second output of the second sense amplifier. A global sense amplifier is coupled to the global data line.

Non-volatile memory having a static verify-read output data path

A read reference level of a plurality of read reference is determined for a set of bit cells of a non-volatile memory array. An indicator of the read reference level is stored in a non-volatile storage location associated with the set of bit cells. The indicator of the read reference level is accessed in response to a read access operation to the set of bit cells and a value stored at a memory location of the set of bit cells is sensed based on the indicator of the read reference level, whereby the memory location of the set of bit cells is associated with the read access operation.

Memory device with retained indicator of read reference level

An integrated circuit () comprises a plurality of non-volatile memory cells () and a charge distribution ramp rate control circuit (). Each memory cell of the array () includes a charge storage region and a plurality of terminals. The charge distribution ramp rate control circuit includes a capacitor () having a first plate electrode coupled to at least one terminal of the plurality of terminals, and a second plate electrode. The charge distribution ramp rate control circuit further includes a bandgap generated current source () for providing a reference current to determine a ramp rate of a voltage at the at least one terminal.

Integrated circuit featuring a non-volatile memory with charge/discharge ramp rate control and method therefor

A level shifter circuit includes first and second cross-coupled P channel transistors, first and second cross-coupled N channel transistors, and first and second inverters. The first and second P channel transistors are coupled to receive a first power supply voltage. The first and second cross-coupled N channel transistors are coupled to the first and second P channel transistors. The first and second inverters are coupled to the first and second N channel transistors and are coupled to receive a second power supply voltage that is lower than the first power supply voltage. The first and second N channel transistors have a lower, substantially zero volts, threshold voltage and can be controlled by a low voltage signal while limiting a leakage current.

Level shifter

A program voltage is applied to the drain electrode of a floating gate transistor to program the floating gate transistor. Concurrent with the application of the program voltage, a current based on the voltage at the source electrode of the floating gate transistor is compared with a threshold current to verify the programming of the floating gate transistor. When the bit cell current falls below the threshold current, the floating gate transistor is considered to be sufficiently programmed and the next floating gate transistor to be programmed is selected. Further, the program voltage supply emulates the selection circuitry used to select between the bit cells so as to model the voltage drop caused by the selection circuitry between the program voltage supply and the drain electrode of the floating gate transistor being programmed. The program voltage supply adjusts the output program voltage based on the modeled voltage drop.

Concurrent programming and program verification of floating gate transistor

A method and apparatus for random-access scan of a network of dynamic logic or N-NARY logic that includes sequentially clocked precharge logic gates and one or more scan gates ( ) driven by multiple overlapping clock signals generated from a clock generation circuit ( ) coupled to a clock spine ( ). Each clocked precharge logic gate and each scan gate include a logic tree ( ) with one or more evaluate nodes, a precharge circuit ( ), an evaluate circuit ( ), and one or more output buffers ( ). Each scan gate further includes a scan circuit ( ) that accepts scan control signals ( , and ) and couples to one or more scan registers ( ) in a RAM-like architecture. Scan control signals operate to capture the state of the output buffers of the scan gate, and to force the output buffers of the scan gate to a preselected level.

Dynamic logic scan gate method and apparatus

An apparatus and method for operating a non-volatile memory including an array of bit cells. A selection is made between an operational power supply and a test power supply, the test power supply being on-chip programmable. The non-volatile memory is operated in a operational mode if the operational power supply is selected, and in a test mode if the test power supply is selected.

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Austin, TX, United States of America

David W Chrudimsky