Enhanced Memory Systems, Inc.

International Business Machines Corporation

David W Bondurant

Kenneth J Mobley

Michael Peters

Bruce Grieshaber

David Fisch

Oscar Frederick Jones, Jr

Steven William Tomashot

Jim L Rogers

A packet-based dynamic random access memory (&ldquo;DRAM&rdquo;) device incorporating an on-chip row register cache which is functional to reduce the initial device latency, reduce &ldquo;page miss&rdquo; latency and reduce chip layout overhead by reducing bus sizes and the level of required multiplexing and demultiplexing compared to Rambus&reg; Direct RDRAM&trade; (trademarks, of Rambus, Inc., Mountain View, Calif.) devices. In accordance with an embodiment of the present invention, the row register cache and a separate write path, or bus, are integrated into each DRAM bank serving to improve DRAM latency parameters and pipeline burst rate. The row register holds &ldquo;read&rdquo; data during burst reads to allow hidden precharge and same bank activation to minimize &ldquo;page miss&rdquo; latency. The faster pipelined burst rate simplifies Direct RDRAM multiplexer/demultiplexer logic and reduces internal data bus size by 50%.

Packet-based integrated circuit dynamic random access memory device incorporating an on-chip row register cache to reduce data access latencies

A packet-based dynamic random access memory (&ldquo;DRAM&rdquo;) device incorporating an on-chip row register cache which is functional to reduce the initial device latency, reduce &ldquo;page miss&rdquo; latency and reduce chip layout overhead by reducing bus sizes and the level of required multiplexing and demultiplexing compared to Rambus&reg; Direct RDRAM&trade; (trademarks, of Rambus, Inc., Mountain View, Calif.) devices. In accordance with an embodiment of the present invention, the row register cache and a separate write path, or bus, are integrated into each DRAM bank serving to improve DRAM latency parameters and pipeline burst rate, The row register holds &ldquo;read&rdquo; data during burst reads to allow hidden precharge and same bank activation to minimize &ldquo;page miss&rdquo; latency. The faster pipelined burst rate simplifies Direct RDRAM multiplexer/demultiplexer logic and reduces internal data bus size by 50%.

A double data rate (&ldquo;DDR&rdquo;) synchronous dynamic random access memory (&ldquo;SDRAM&rdquo;) device incorporating a static random access memory (&ldquo;SRAM&rdquo;) cache per memory bank that provides effectively double peak data bandwidth, optimizes sustained bandwidth and improves bus efficiency as compared with conventional DDR SDRAM devices. The memory device disclosed provides effectively faster basic DRAM memory latency parameters, faster page &ldquo;hit&rdquo; latency, faster page &ldquo;miss&rdquo; latency and sustained bandwidth on random burst reads, faster read-to-write latency and write-to-read latency, hidden precharge, hidden bank activate latency, hidden refresh and hidden write precharge during a read &ldquo;hit&rdquo;.

Double data rate synchronous dynamic random access memory device incorporating a static RAM cache per memory bank

An enhanced bus turnaround integrated circuit dynamic random access memory (&ldquo;DRAM&rdquo;) device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround (&ldquo;ZBT&rdquo;), or pipeline burst static random access memory (&ldquo;SRAM&rdquo;) devices. The enhanced bus turnaround DRAM device of the present invention provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost approaching that of straight DRAM memory. Through the provision of a &ldquo;Wait&rdquo; pin, the enhanced bus turnaround device of the present invention can signal the system memory controller when additional wait states must be added yet still provide virtually identical data access time performance to that of ZBT SRAM for all Read and Write operations with a burst length of four or greater. Use of master/slave and inhibit pins.

Enhanced bus turnaround integrated circuit dynamic random access memory device

A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture and a programmable caching policy includes a synchronous dynamic random access memory (SDRAM) bank, a synchronous static randomly addressable row register, a select logic gating circuit, and mode register for programming of the cached SDRAM to operate in a Write Transfer mode corresponding to a Normal Operation mode of a standard SDRAM during a Write cycle, and to operate in a No Write Transfer mode according to an alternate operation mode during a Write cycle, thereby operating under a first and a second caching policy, respectively. The SDRAM includes a row decoder for selecting a row of data in a memory bank array, sense amplifiers for latching the row of data selected by the row decoder, and a synchronous column selector for selecting a desired column of the row of data. The row register stores a row of data latched by the sense amplifiers and the select logic gating circuit, disposed between the sense amplifiers and the row register, selectively gates the row of data present on the bit lines to the row register in accordance to particular synchronous memory operations being performed.

Cached synchronous DRAM architecture having a mode register programmable cache policy

An enhanced bus turnaround integrated circuit dynamic random access memory ('DRAM') device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround ('ZBT'), or pipeline burst static random access memory ('SRAM') devices. The enhanced bus turnaround DRAM device of the present invention provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost approaching that of straight DRAM memory. Through the provision of a 'Wait' pin, the enhanced bus turnaround device of the present invention can signal the system memory controller when additional wait states must be added yet still provide virtually identical data access time performance to that of ZBT SRAM for all Read and Write operations with a burst length of four or greater. Use of master/slave and inhibit pins.

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Colorado Springs, CO, United States of America

David W Bondurant