International Business Machines Corporation

David W Blum

John E Gersbach

Shiu Chung Ho

A duty-cycle correction circuit corrects a clock with arbitrary duty-cycle to a 50% duty-cycle clock, with its original frequency. The device acts to translate a non-50% duty-cycle clock to an accurate 50% duty-cycle clock by utilizing a divide-by-2 frequency divider and a multiply-by-2 clock doubler to achieve conversion. The duty-cycle correction circuit increases the translation back to its original frequency while using an analog negative feedback to maintain an accurate 50% duty cycle.

Duty-cycle correction circuit

A duty cycle correction circuit that facilitates correction of clock signal duty cycles, including correcting for errors introduced by intervening devices in the clock signal distribution network. The duty cycle correction circuit of the preferred embodiment comprises a clock chopper circuit, a duty cycle comparator circuit, and a control circuit. The duty cycle comparator circuit compares the duty cycle of the clock signal with the duty cycle of a reference signal. The control circuit adjusts the clock chopper circuit based upon the duty cycle comparison, resulting in an output with a corrected duty cycle.

Clock signal duty cycle correction circuit and method

This is a detector system comprised of a differential driver circuit, a driver output stage and splitter circuit and a multiplexor. The driver circuit employs a bridge circuit that converts input logic voltages to lower voltage differential outputs by utilizing a pair of current switch transistors coupled to the bridge circuit. The bridge circuit is comprised of cross coupled transistors whose inputs are coupled to matched true and complement input logic voltages that swing between zero volts and the power supply voltage. The bridge transistors convert the differential logic input voltage swings to smaller values that are compatible with driving the splitter and multiplexor circuits coupled thereto. The driver circuit and the splitter circuit share the driver output transistors which are arranged in parallel pairs. These pairs are coupled to respective output lines whose physical state is to be determined and to the multiplexor which is an emitter coupled switch coupled to emitter follower transistors which are, in turn, connected to respective output lines so that the output voltage of the output transistors can be used to determine if the output lines are open.

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Essex Junction, VT, United States of America

David W Blum