Rockwell International Corporation

Amsc Subsidiary Corporation

Civco Medical Instruments, Inc.

Motient Communications Inc.

David W Best

Jeffrey D Russell

Santanu Dutta

Dennis W Sutherland

Thomas A Trebs

Craig Joseph Cermak

Brett Severence

Kevin L McGahee

John D Bates

David F Schultz

A packet switched multi-mode mobile communication network and fixed and mobile devices for use therewith are disclosed. Each of the mobile vehicle equipment and a base station packet switch are coupled to respective data terminal equipment which generates packet data messages. The packet data messages have message characteristics associated therewith. Each of the mobile vehicle equipment and the base station packet switch have an intelligent switching node incorporated therein for selecting which of a plurality of radio frequency transmission paths to use in transmitting the packet data message to the other of the mobile vehicle equipment and the base station packet switch. Each of the plurality of radio frequency transmission paths has transmission path characteristics associated therewith. The intelligent switching nodes select the radio frequency transmission path as a function of the message characteristics of the packet data message and as a function of the transmission path characteristics of the plurality of radio frequency transmission paths.

Wide area mobile communication networks with multiple routing mode options

A needle guide for use in imaging analysis, such as ultrasound analysis, is provided having a mounting base secured to the imaging instrument. A needle guide is configured to be removably secured to the pivoting portion of the mounting base. The needle guide has a rotational needle retainer member that is configured to retain a needle by securing the needle within a slot on the needle guide.

Multiple angle needle guide

Wide area mobile communication networks with multiple routing mode

A self-timed bus arbitration and digital data transfer system is provided for a computer network having multiple master and slave devices sharing a digital data bus. Each master device includes a bus arbitration logic circuit having a time delay element. Each master contending for access to the data bus outputs an identifier on signal lines connecting the master devices. After a period of time comprising the slowest master's operational delay, the bus arbitration circuits determine, on a prioritized basis, which particular master shall have access to the data bus at that time. Upon gaining access, the particular master provides a request signal on a control line connecting the master and slave devices and provides an address on an address bus that may be multiplexed with the data bus. After each slave has decoded the address, as determined by the slowest slave's delay, an acknowledge signal is provided on the control line to the particular master so that data transfer may proceed to/from the selected slave. When the data transfer is complete, the selected slave signals the particular master to release the data bus for subsequent operations. Bus arbitration for a subsequent operation may be performed during the current data transfer. All operations are self-timed in that they do not require a bus clock, but they are constrained through wire-OR logic circuitry by the slowest device connected to the system, which includes all delays resulting from bus length, buffers, and environmental conditions.

Method and apparatus for self-timed digital data transfer and bus

A self-timed bus arbitration and digital data transfer system is provided for a computer network having multiple master and slave devices sharing a digital data bus. Each master device includes a bus arbitration logic circuit having a time delay element. Each master contending for access to the data bus outputs an identifier on signal lines connecting the master devices. After a period of time comprising the slowest master's operational delay, the bus arbitration circuits determine, on a prioritized basis, which particular master shall have access to the data bus at that time. Upon gaining access, the particular master provides a request signal on a control line connecting the master and slave devices and provides an address on an address bus that may be multiplexed with the data bus. After each slave has decoded the address, as determined by the slowest slave's delay, an acknowledge signal is provided on the control line to the particular master so that data transfer may proceed to/from the selected slave. When the data transfer is complete, the selected slave signals the particular master to release the data bus for subsequent operations. Bus arbitration for a subsequent operation may be performed during the current data transfer. All operations are self timed in that they do not require a bus clock, but they are constrained through wired-OR logic circuitry by the slowest device connected to the system, which includes all delays resulting from bus length, buffers, and environmental conditions.

A fault tolerant, fail-active computer system comprises a Redundancy Management Unit (RMU) and a plurality of Dual-Port Message Buffers (DPBs) connecting each of a corresponding plurality of communication channels to the RMU. Each DPB includes a message channel interface, a dual-port RAM, a word counter, a page FIFO, a message header FIFO, and a message buffer control circuit. The RMU includes word comparators, 3-state gates, a message comparison control circuit, and a voted message FIFO. Under software control, the RMU and DPBs perform the functions of management of asynchronous redundant digital messages, sorting of redundant messages received in arbitrary order, synchronization of distributed computing elements, comparison of data words of arbitrary bit length, and configuration control of active channels and communication path redundancy.

Apparatus for management, comparison, and correction of redundant

Apparatus as disclosed which comprises a register normally operable in the parallel data in/parallel data out mode but which has control mechanisms for allowing it to be converted to a serial data in/serial data out register. This register comprises part of a register based state machine. When the register is locked in a given mode so that a predefined control bit pattern is maintained within the register while the rest of the state machine operates in a normal manner, the control bit pattern is iteratively executed which in turn allows the use of an oscilloscope to observe signals in the signal transmission path of the state machine.

Repetitious logic state signal generation apparatus

A logical AND and logical OR gate are utilized in conjunction with two signals forming bits to be added for ascertaining the value of generate and propagate signals. The generate signal is passed to the output whenever the carry input is a logic zero and the propagate signal is supplied to the output whenever the carry signal is a logic one. This simplification of the approach to generating ripple carry signals substantially reduces the number of transistor to a value of about one-half that utilized in the prior art.

Apparatus for and method of generation of ripple carry signals in

Synchronously clocked gating apparatus is illustrated for time multiplexing signals into and out of a register simultaneously whereby a single pin can be utilized for the two sets of data transfer rather than the two pins required in the prior art.

Single pin time-sharing for serially inputting and outputting data from

When a state machine such as a computer is inoperative, the flow of data can occur in so many different ways that it is at times difficult to ascertain the portions of the state machine that are causing the problems. Whether the problems are caused by original design or later failure of components, the present invention can determine at least the general area of the problem and often the specific bit introducing the problem, by setting a predefined control bit pattern into a register and ascertaining whether or not the bit pattern returned to the register after a predefined sequence of operations matches design expectations. As illustrated, this may take the form of serially inserting data into a normally parallel operated register to form the predefined control bit pattern, which then is applied to a sequencer whose output address is used to address a word in ROM, and the addressed word as well as the address itself, is loaded into the register. The address and addressed word are then compared with design expectations to determine whether or not there is a problem with that particular instruction or that particular location in ROM.

Method and apparatus for testing and verifying the operability of

Circuits are illustrated using CMOS design techniques for incorporating N and P channel transistors into a circuit to obtain the functions of exclusive OR and exclusive NOR signal generation. This is accomplished by utilizing a given logic value signal as a control signal to pass the other input signal for three of the four possible logic value conditions. The fourth condition must generate the output signal from a selected one of the input signals, through the use of an inverter.

Apparatus and method for providing a logical exclusive OR/exclusive NOR

A circuit is illustrated for performing an increment function wherein a savings of parts is obtained by using an inverter for two different functions thereby decreasing land area required for implementing the integrated circuit on a chip.

Digital binary increment circuit apparatus

Apparatus is presented for logically combining two input signals in parallel operations to provide AND and OR as well as Exclusive OR outputs as part of the ALU function in a digital computer. The carry function is used in combination with the already generated signals of AND, OR and Exclusive OR to provide a carry output signal and a SUM signal through logic combining techniques. Thus, the entire ALU output is obtained in two stages of time delay and a great savings in components. In some computers, the outputs need to be passed through a four to one multiplexer to select the desired output.

Parallel operating mode arithmetic logic unit apparatus

A circuit for multiplexing a plurality of input signals to a single output signal through the use of N and P channel FETs whereby complementary switching circuitry results in a minimization of power usage in either the active or static circuit conditions. This is accomplished by using a feedback technique and area sizing of the FETs to obtain optimum operational results in addition to the minimal power requirements.

Efficient means for implementing many-to-one multiplexing logic in

The typical gating means (four) in a master/slave flip flop are duplicated for each input signal to be multiplexed through the flip flop and a separate control signal is applied to each set of four gating means for determining which of the plurality of input signals is to be passed through the flip flop. While for a single flip flop there is no advantage in reduction of components, when the flip flop is used as one of a plurality of flip flops such as in a register, the reduction of components (used for multiplexing) is very significant.

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Marion, IA, United States of America

David W Best