Xilinx, Inc.

Ionu Security, Inc.

Other

David W Bennett

Jeffrey M Mason

Prasanna Sundararajan

Alan M Frost

Timothy E Beres

Ralph D Wittig

Sundararajarao Mohan

Andrew Richard Putnam

Satish R Ganesan

Robert Gwilym Dimond

John D Corbett

Bruce E Talley

Usha Prabhu

Lauren B Wenzl

Paul Franklin Vernon, Ii

Steve E Lass

Approaches for synchronizing data files across multiple systems are described. A user-specified value of a threshold indicative of a quantity of data is input to a computer processor and stored in processor-readable memory on one of the systems. A set of files of the replicated files that are unsynchronized between the one system and another system of the systems is determined, along with a quantity of data to be synchronized for the set of files. The files in the set of files are synchronized between the one system and the other system in response to the quantity of data to be synchronized satisfying the value of the threshold. Fewer than all of the set of files are synchronized in response to the quantity of data to be synchronized not satisfying the threshold.

User controlled file synchronization limits

Approaches for searching for key terms in a plurality of files include associating a respective key map with each file of the plurality of files in memory of a server. Each key map includes a plurality of bit values and each bit value indicates for a key term whether or not the key term is present in the associated file. The server inputs a search map, and the search map includes a plurality of bit values. Each bit value in the search map indicates for a key term whether or not the key term is a key term to search. The server determines for each key map, whether or not the key map satisfies the search map. Data indicating each file of the plurality of files having an associated key map that satisfies the search map is output by the server.

Searching data files using a key map

In an approach for protecting against use of clones of electronic devices, a first sequence value is initialized on the server and an equal second sequence value is initialized on an electronic device. In response to a first login request to the server from a user operating the electronic device, the first and second sequence values are compared. If the values are equal, processing of the login process continues. Otherwise, the login request is rejected. If the login is successful, a next value is computed for the first and second sequence values, and the next first and second sequence values are stored on the server and on the electronic device, respectively.

Protection against unauthorized cloning of electronic devices

Approaches for deduplicating data include generating a first key from plain text data of a first data element. The first data element is encrypted using the first key. The first key is compared to each key of a plurality of previously stored keys, which are associated with other encrypted data elements. In response to the first key matching a second key of the plurality of previously stored keys, the encrypted first data element is compared to the other encrypted data element associated with the second key. In response to the encrypted first data element matching the other encrypted data element, the first key is associated with the other encrypted data element, and the encrypted first data element is discarded.

Data deduplication with encryption

Methods and systems are disclosed for generating a public-private key pair. A programmed processor displays a plurality of questions and inputs two or more answers to two or more of the plurality of questions in response to user input. The processor computes the public-private key pair as a function of the two or more answers to the two or more questions and stores the public-private key pair in memory coupled to the processor.

Generation of public-private key pairs

Approaches for protecting a data element are disclosed. The method includes encrypting the data element with a first key on a first client system. A set of permissions is stored in association with the encrypted data element, and a first signature is generated from the set of permissions for the data element. The first key is encrypted with a second key on the first client system. The encrypted first key is stored in association with the encrypted data element, and the second key is encrypted with a public key of a public-private key pair of a first user on the first client system. The first signature and the encrypted second key are transmitted from the first client system to a server system for storage.

Protection of shared data

Approaches for caching addressable items in a multiprocessor system. Instructions are cached in a plurality of first-level instruction caches respectively coupled to a plurality of processors of the multiprocessor system. First-type data items are cached in a plurality of first-level data caches respectively coupled to the plurality of processors. Second-type data items are cached in a second-level cache and are not cached in any of the plurality of first-level data caches.

Processor and cache arrangement with selective caching between first-level and second-level caches

In one embodiment, a system for secure application hosting is provided. The system includes a memory, a first processor coupled to the memory, a second processor coupled to the first processor via a bus, and a data storage device and a network interface coupled to the second processor. The second processor is configured to perform cryptographic processing to provide an encrypted domain, in which the network interface and data storage device operate, and an unencrypted domain, in which the processor and memory operate.

Secure cloud computing infrastructure

Generation of cache architecture from a high-level language description is described. A description of an application in a high-level programming language is obtained. A data flow representation is generated from the description suitable for providing an implementation in hardware. The generating includes: identifying accesses to memory associated with the description; determining that at least a portion of the accesses to memory do not have one or more data dependencies for locally cacheable data; and assigning the portion to a distributed cache.

Generation of cache architecture from a high-level language description

Approaches for creating a pipelined circuit design from a high level language (HLL) specification. In one embodiment, the HLL specification is translated into an intermediate level language specification of operations of the pipelined circuit design, and a data dependency graph of the operations is created. A sequence of operations that is bounded by two write operations and that has no intervening write operations between the two write operations is identified, along with two or more read operations within the sequence. A pipelined design specification is generated from the dependency graph and hardware components associated with the operations in the intermediate level language specification. At least two of the components corresponding to the two or more read operations access a memory in parallel, and each component corresponding to the two or more read and the two write operations requires a synchronization token as input and outputs a synchronization token upon completion of the operation.

Synchronization of parallel memory accesses in a dataflow circuit

Approaches for generating a hardware specification from a high-level language (HLL) program. In one approach, a method determines separate accesses in the HLL program to multiple consecutively addressed data items. The HLL program is compiled into an intermediate language program to include one or more instructions that perform functions on the multiple consecutively addressed data items and one or more memory access instructions that reference the consecutively addressed data items. The method generates a hardware specification from the intermediate language program. The hardware specification includes a cache memory that caches the consecutively addressed data items and that accesses the consecutively addressed data items in response to a single access request. The specification further includes one or more hardware blocks that implement the functions of the instructions in the intermediate language program. At least one of hardware blocks has access to the multiple consecutively addressed data items in parallel.

Optimization of cache architecture generated from a high-level language description

Approaches for synchronizing memory accesses in a dataflow computing system. A compute operation in the dataflow computing system is commenced in response to availability in a dataflow memory of each operand that is required to perform the compute operation. Output data from a compute operation is stored in the dataflow memory at completion of the compute operation. Write and read operations are supported for accessing an external memory. Accesses to the external memory are synchronized by storing synchronization tokens in the data flow memory. Each synchronization token signals when an address in the external memory may be accessed.

Synchronization of external memory accesses in a dataflow machine

Approaches for generating a design of an electronic system are disclosed. In one approach, for each of one or more components of a first specification of the design, an error mitigation technique is selected from among multiple different error mitigation techniques in response to user-specified data associated with the first specification of the design. A second specification of the design is automatically generated from the first specification. The second specification includes error mitigation logic corresponding to each selected error mitigation technique for each of the one or more components. The second specification of the design is stored for subsequent processing.

Methods for automatically generating fault mitigation strategies for electronic system designs

A floating-point processing unit for a succession of floating-point operations. An exponent adjustor is coupled to receive numerical inputs and configured to generate first adjusted values from the numerical inputs. The first adjusted values have equivalent exponents as between corresponding first adjusted values. A first operation specific floating-point processing unit (OFPU) is coupled to receive the first adjusted values and includes first arithmetic circuitry configured for a first floating-point operation on the first adjusted values to provide first numerical results. The first numerical results are not normalized prior to a second floating-point operation.

Floating-point processing unit for successive floating-point operations

Various approaches are described for implementing a high-level programming language program in hardware and software components. In one approach, a method comprises compiling the high-level programming language program into a target language program that includes a plurality of functional elements. Execution of the target language program is profiled to obtain execution counts of the functional elements. A subset of the functional elements are selected for implementation in programmable resources of a programmable device based on the profile data and availability of programmable resources. A bitstream is generated to implement a first sub-circuit that performs functions of the subset of functional elements, and the subset of functional elements is removed from the target language program. The programmable device is configured with the bitstream. The target language program is provided for execution by a processor.

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Longmont, CO, United States of America

David W Bennett