Harris Corporation

Datotek, Inc.

David W Abmayr

Barrie O Morgan

James O Rozell

The specification discloses a system and method for authenticating a message recipient prior to transmission of a message and for authenticating the message content after receipt of the message. A randomized character or character sequence is initially enciphered at the authenticator station and stored. The enciphered character is transmitted to the message recipient. The enciphered character is deciphered by the message recipient to reproduce the randomized character. The randomized character is reenciphered by the message recipient and transmitted back to the authenticator station. The reenciphered character is deciphered and the stored randomized character is compared with the deciphered character. The message recipient is authenticated if the stored randomized character exactly compares with the deciphered character. In order to authenticate the message after receipt, polynomial block check characters are accumulated from the message. The block check characters are enciphered according to a predetermined enciphering scheme and transmitted to a remote location, along with the message. The message is received at the remote location and polynomial block check characters are accumulated in response to the received message. Enciphered block check characters are received and deciphered according to the reverse of the predetermined enciphering scheme. The accumulated block check characters are compared with the deciphered block check characters and the message is authenticated if the compared characters are the same.

Recipient and message authentication method and system

A selective memory addressing scheme employs a programmable read only memory (PROM) which responds to the opcode of the next instruction to be executed and supplies control information to memory module selection registers.The memory module selection registers operate in conjunction with the internal address registers to provide the necessary steering information for properly addressing the intended memory location. The PROM is programmed in accordance with the instruction set by which the processor operates and is coupled to decode the opcode contents of the instruction register that has been loaded, in a lookahead fashion, with the instruction following the instruction presently being executed by the central processing unit. The PROM has a first output that defines whether or not a second output of the PROM is to be used to select the memory module containing the operand to be referenced in the execution of the next instruction. This second output of the PROM is of a code size required to identify any one of the modules in the bank. The PROM has a third output that may be used to increment the location counter based upon the length of the next instruction. Where the second output of the PROM is not to be used to select the memory module containing the operand to be referenced, the first output of the PROM has a state such that it gates out information stored in a program status word register to identify the memory module containing the operand of the next instruction to be executed. To provide for direct CPU intervention in the execution of instructions, such as may occur in the case of an interrupt, prescribed bits of the CPU data bus may be selectively coupled to the module selection circuitry, so that the opcode-dependent operation of the PROM is bypassed and direct CPU selection within the memory bank may be achieved.

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Carrollton, TX, United States of America

David W Abmayr